hi, systemverilog support packed array, such as
sveditor currently report error. could you please fix this. thanks a lot.
Unfortunately, the example you provide works for me. Can you provide a more-complete example that shows the parse error? It should look something like:
module m; // module or class
i think i found the problem.
In my code, it actually is
once i change wire to reg or logic, then the error sign goes away.
Hope you can replicate the problem i see. I can use "logic" to replace "wire" for now.
Thanks for the clarification. I've checked a few cases, and the one case where I can get SVEditor to show a failure is when a wire-type variable is declared within a task/function context:
function void foo;
Can you confirm this is the scenario you're seeing?
What simulator are you using? I'm using Mentor Questa, which flags this scenario as an error.
Thanks and Regards,
this is my code, it passes Questa, and works. but sveditor flags error on wire fred;
reg a = 5;
reg b = 7;
assign fred = a;
assign fred = b;
assign c = fred + fred;
probably i am not using the latest version. sorry for the confusion
somehow my type assist is not working now. i mean if i type ctrl+space, nothing pop up.
ok i fixed it. thanks.
can i delete this stupid thread i created?