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That's interesting. I will take a look.
> I found the most probable issue for your synthesis problems. In the
> file "rtl/sram_interface.v" there is generic code, which does not
> compile properly using XST (Xilinx Synthesis Tool).
> One issue is the $clog2 function (used to calculate the
> counter/address bus width for the FIFO/memory from the memory size)
> inside "rtl/cdc.v" and commented out in "rtl/sram_interface.v".
> Inside "rtl/sram_interface.v" is the 6kB memory for which XST
> consumes 16 blocks, instead of the actually necessary 12. This is
> probably why your project does not fit.
For BRAMs is it usually possible to simply make a big register array,
or is there usually a vendor tool to generate a special "BRAM core" a.
la. Xilinx DCMs.
> This two Xilinx specific exceptions are inside an ifdef/endif
> block, and the macro "XC3S250E" must be available for this code to
> compile properly using XST. One way to solve this is to define this
> macro at the beginning of this files: `define XC3S250E The other
> option is to add macro definitions to the Xilinx project file, this
> is used in the project on my repo. Here are some instructions
> (under Verilog Macros):
Advanced settings have to be enabled for the option to be present:
so in terms of my hopes of universal configuration, I'd like to
be able to have a vendor macro: XILINX, ALTERA etc. a FPGA class
macro: XC3S, or SPARTAN3E etc. and a device specific macro XC3S250E.
The current use of the XC3S250E isn't quite right because it would
require a different constant for every device we ever port to.
> (Ordb2a-ep4ce22<http://opencores.org/or1k/Ordb2a-ep4ce22>) or can
> I have created some more generic test environment code (not used
> much yet), and decided to start porting to a board I own
> borrow (Terasic
> DE1<http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=83>). For
> this purpose I will revive the UART interface.That makes sense. I believe the sigrok ols driver supports
SUMP-over-serial out of the box.
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