Hi Christoph,

Thanks for your comments.

Regards,
Iztok Jeras


On Mon, Jul 15, 2013 at 11:27 PM, Christoph Zimmermann <nussgipfel@brain4free.org> wrote:
Hi

> I was asking myself, what would a dedicated external trigger add to
> the project and I could not find a positive answer.
>
> I checked a few documents for expensive LA, and it seems the only
> purpose of an external trigger input is to have a dedicated BNC or
> similar connector for interfacing the LA to other devices from the
> same vendor.
>
> In our case one of the input signals could be used instead of a
> dedicated trigger input. In any case, to properly use an external
> trigger, some edge detection is necessary. This and more can be done
> with generic trigger code, which is applied to all IOs.

Over the last days I was thinking about your question.
Yes, you are right, the external trigger input is "just another logic
probe".

The "only" difference is, that it has a BNC connector and has a fixed
voltage level (typ. +5 V) independent of logic input level (TTL, ECL,
1,2 V CMOS, LVDS...).

So from your point of view there is no external trigger input. For a
hardware designer there is one.

So I can treat this as a regular signal internally, but on the edge, near IO pins this would be a separate signal.
 


In this context:
Just to be sure: A trigger output is something that is essential
(Needed for every kind of more complex measurement setup).

Yes, I understand this part.
 

> The other question is regarding external clock. Do tools from any
> vendor support external clocking for the SPI protocol, where the
> clock is silent if slave select is not active. The problem is, if
> there is no clock, the edge on the slave select signal can not be
> detected, without clock it is also not possible to push data through
> input pipeline stages (before clock domain crossing). Maybe this is
> not the bast example, but the question remains, how sampling on
> external clock works, if this clock is not available while the system
> is idle.

Absoultely no idea how this is handled or if it is handled.

I will try to read the documentation for a device with a SPI slave port and a separate internal clock (I already know SPI Flash), for example an ARM SoC, since the problem is similar.
 

The first part "the edge on the slave select signal can not be
detected" is not problematic, we can use the level trigger (because we
are synchronous to the spi clock).

If the bus is sampled on SPI clock, and this only toggles while slave select is active, then there will be no clock edges while slave select is inactive.
 
But the question about sampling is a valid one.

While reading the documentation of some contemporary LA, one idea came to mind. It is possible to simultaneously sample the same signals using a synchronous and an asynchronous clock. The synchronous part is used for sampling data at the moment the eye is most open, the asynchronous part is used for other signals, But for now I have no good ideas how to handle proper alignment of this signals for GUI display, or protocol processing. This will definitely not be a feature soon.
 

Hmm, the same situation applies for I2C too.

I2C is actually not such an issue, since the protocol is slow and the data rate is low compared to signal rising times. So I2C is (can be) always samples asynchronously.
 

Greetings,
nuess0r

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