#53 PIC16F684 support

closed-out-of-date
nobody
None
5
2006-04-07
2006-01-10
Anonymous
No

Here's a patch to add support for the PIC16F684. Two
main changes were required:

src/pic/device.c:
p16f684.inc (from GPUTILS / Microchip)

The change to device.c just tells SDCC what the spec of
the 16F684 microcontroller is, and the change to
p16f684.inc is to allow the perl script (can't remember
what it's called) to successfully generate a correct
version of pic16f684.h (also attached, for convenience)
for inclusion in the C progs.

I've submitted changes to the maintainer of "picp"
(Linux command line interface to the Microchip
"Picstart Plus" programmer) in order to ensure that the
the resultant hex file from SDCC/GPUTILS can be burned
to the PIC. These changes are attached here too for
convenience and completeness, but are not required for
the SDCC change (obviously!).

Discussion

  • Logged In: YES
    user_id=884387

    Whoops.. files did not get attached.. Here is device.c
    change.. others will follow:

    static PIC_device Pics[] = {
    //16F684 added by Colm O Flaherty, based on Microchip
    datasheet 41202C page 9,
    //2.0) Memory Organisation - 2.1) Program Memory
    Organisation - "The PIC16F684
    //has a 13-bit program counter capable of addressing an 8k
    x 14 program memory
    //space. Only the first 2k x 14 (0000h-07FFh) for the
    PIC16F684 is physically
    //implemented"...
    {
    {"p16f684", "16f684", "pic16f684", "f684"}, /* processor
    name */
    (memRange *)NULL,
    (memRange *)NULL,
    0, /* max ram address (calculated) */
    0x7ff, /* default max ram address */
    0x80, /* Bank Mask: there are 2 banks, and bit
    7 of the address */
    /* determines which bank houses the data memory */
    },

     
  • Logged In: YES
    user_id=884387

    Here's the required updated version of p16f684.inc:

    My changes are labelled version 1.04

    LIST
    ; P16F684.INC Standard Header File, Version 1.04
    Microchip Technology, Inc.
    NOLIST

    ; This header file defines configurations, registers, and
    other useful bits of
    ; information for the PIC16F684 microcontroller. These
    names are taken to match
    ; the data sheets as closely as possible.

    ; Note that the processor must be selected before this file is
    ; included. The processor may be selected the following ways:

    ; 1. Command line switch:
    ; C:\ MPASM MYFILE.ASM /PIC16F684
    ; 2. LIST directive in the source file
    ; LIST P=PIC16F684
    ; 3. Processor Type entry in the MPASM full-screen
    interface

    ;==========================================================================
    ;
    ; Revision History
    ;
    ;==========================================================================
    ;1.00 03/20/03 Original
    ;1.01 08/04/03 Updated CMCON1 address
    ;1.02 08/05/03 Updated names to match datasheet
    ;1.03 08/11/03 Updated ULPWUE bit name to match datasheet
    ;1.04 12/28/05 Updated COMCON* reference in comments to CMCON*
    ;==========================================================================
    ;
    ; Verify Processor
    ;
    ;==========================================================================

    IFNDEF __16F684
    MESSG "Processor-header file mismatch. Verify
    selected processor."
    ENDIF

    ;==========================================================================
    ;
    ; Register Definitions
    ;
    ;==========================================================================

    W EQU H'0000'
    F EQU H'0001'

    ;----- Register
    Files------------------------------------------------------

    INDF EQU H'0000'
    TMR0 EQU H'0001'
    PCL EQU H'0002'
    STATUS EQU H'0003'
    FSR EQU H'0004'
    PORTA EQU H'0005'

    PORTC EQU H'0007'

    PCLATH EQU H'000A'
    INTCON EQU H'000B'
    PIR1 EQU H'000C'

    TMR1L EQU H'000E'
    TMR1H EQU H'000F'
    T1CON EQU H'0010'
    TMR2 EQU H'0011'
    T2CON EQU H'0012'
    CCPR1L EQU H'0013'
    CCPR1H EQU H'0014'
    CCP1CON EQU H'0015'
    PWM1CON EQU H'0016'
    ECCPAS EQU H'0017'
    WDTCON EQU H'0018'
    CMCON0 EQU H'0019'
    CMCON1 EQU H'001A'

    ADRESH EQU H'001E'
    ADCON0 EQU H'001F'

    OPTION_REG EQU H'0081'

    TRISA EQU H'0085'
    TRISC EQU H'0087'

    PIE1 EQU H'008C'

    PCON EQU H'008E'
    OSCCON EQU H'008F'
    OSCTUNE EQU H'0090'
    ANSEL EQU H'0091'
    PR2 EQU H'0092'

    WPU EQU H'0095'
    WPUA EQU H'0095'
    IOC EQU H'0096'
    IOCA EQU H'0096'

    VRCON EQU H'0099'
    EEDAT EQU H'009A'
    EEDATA EQU H'009A'
    EEADR EQU H'009B'
    EECON1 EQU H'009C'
    EECON2 EQU H'009D'
    ADRESL EQU H'009E'
    ADCON1 EQU H'009F'

    ;----- STATUS Bits
    --------------------------------------------------------

    IRP EQU H'0007'
    RP1 EQU H'0006'
    RP0 EQU H'0005'
    NOT_TO EQU H'0004'
    NOT_PD EQU H'0003'
    Z EQU H'0002'
    DC EQU H'0001'
    C EQU H'0000'

    ;----- INTCON Bits
    --------------------------------------------------------

    GIE EQU H'0007'
    PEIE EQU H'0006'
    T0IE EQU H'0005'
    INTE EQU H'0004'
    RAIE EQU H'0003'
    T0IF EQU H'0002'
    INTF EQU H'0001'
    RAIF EQU H'0000'

    ;----- PIR1 Bits
    ----------------------------------------------------------

    EEIF EQU H'0007'
    ADIF EQU H'0006'
    CCP1IF EQU H'0005'
    C2IF EQU H'0004'
    C1IF EQU H'0003'
    OSFIF EQU H'0002'
    T2IF EQU H'0001'
    TMR2IF EQU H'0001'
    T1IF EQU H'0000'
    TMR1IF EQU H'0000'

    ;----- T1CON Bits
    ---------------------------------------------------------

    T1GINV EQU H'0007'
    TMR1GE EQU H'0006'
    T1CKPS1 EQU H'0005'
    T1CKPS0 EQU H'0004'
    T1OSCEN EQU H'0003'
    NOT_T1SYNC EQU H'0002'
    TMR1CS EQU H'0001'
    TMR1ON EQU H'0000'

    ;----- T2CON Bits
    ---------------------------------------------------------

    TOUTPS3 EQU H'0006'
    TOUTPS2 EQU H'0005'
    TOUTPS1 EQU H'0004'
    TOUTPS0 EQU H'0003'
    TMR2ON EQU H'0002'
    T2CKPS1 EQU H'0001'
    T2CKPS0 EQU H'0000'

    ;----- CCP1CON Bits
    -------------------------------------------------------

    P1M1 EQU H'0007'
    P1M0 EQU H'0006'
    DC1B1 EQU H'0005'
    DC1B0 EQU H'0004'
    CCP1M3 EQU H'0003'
    CCP1M2 EQU H'0002'
    CCP1M1 EQU H'0001'
    CCP1M0 EQU H'0000'

    ;----- PWM1CON Bits
    -------------------------------------------------------

    PRSEN EQU H'0007'
    PDC6 EQU H'0006'
    PDC5 EQU H'0005'
    PDC4 EQU H'0004'
    PDC3 EQU H'0003'
    PDC2 EQU H'0002'
    PDC1 EQU H'0001'
    PDC0 EQU H'0000'

    ;----- ECCPAS Bits
    --------------------------------------------------------

    ECCPASE EQU H'0007'
    ECCPAS2 EQU H'0006'
    ECCPAS1 EQU H'0005'
    ECCPAS0 EQU H'0004'
    PSSAC1 EQU H'0003'
    PSSAC0 EQU H'0002'
    PSSBD1 EQU H'0001'
    PSSBD0 EQU H'0000'

    ;----- WDTCON Bits
    --------------------------------------------------------

    WDTPS3 EQU H'0004'
    WDTPS2 EQU H'0003'
    WDTPS1 EQU H'0002'
    WDTPS0 EQU H'0001'
    SWDTEN EQU H'0000'

    ;----- CMCON0 Bits
    -------------------------------------------------------

    C2OUT EQU H'0007'
    C1OUT EQU H'0006'
    C2INV EQU H'0005'
    C1INV EQU H'0004'
    CIS EQU H'0003'
    CM2 EQU H'0002'
    CM1 EQU H'0001'
    CM0 EQU H'0000'

    ;----- CMCON1 Bits
    -------------------------------------------------------

    T1GSS EQU H'0001'
    C2SYNC EQU H'0000'

    ;----- ADCON0 Bits
    --------------------------------------------------------

    ADFM EQU H'0007'
    VCFG EQU H'0006'
    CHS2 EQU H'0004'
    CHS1 EQU H'0003'
    CHS0 EQU H'0002'
    GO EQU H'0001'
    NOT_DONE EQU H'0001'
    GO_DONE EQU H'0001'
    ADON EQU H'0000'

    ;----- OPTION Bits
    --------------------------------------------------------

    NOT_RAPU EQU H'0007'
    INTEDG EQU H'0006'
    T0CS EQU H'0005'
    T0SE EQU H'0004'
    PSA EQU H'0003'
    PS2 EQU H'0002'
    PS1 EQU H'0001'
    PS0 EQU H'0000'

    ;----- PIE1 Bits
    ----------------------------------------------------------

    EEIE EQU H'0007'
    ADIE EQU H'0006'
    CCP1IE EQU H'0005'
    C2IE EQU H'0004'
    C1IE EQU H'0003'
    OSFIE EQU H'0002'
    T2IE EQU H'0001'
    TMR2IE EQU H'0001'
    T1IE EQU H'0000'
    TMR1IE EQU H'0000'

    ;----- PCON Bits
    ----------------------------------------------------------

    ULPWUE EQU H'0005'
    SBODEN EQU H'0004'
    NOT_POR EQU H'0001'
    NOT_BOD EQU H'0000'

    ;----- OSCCON Bits
    --------------------------------------------------------

    IRCF2 EQU H'0006'
    IRCF1 EQU H'0005'
    IRCF0 EQU H'0004'
    OSTS EQU H'0003'
    HTS EQU H'0002'
    LTS EQU H'0001'
    SCS EQU H'0000'

    ;----- OSCTUNE Bits
    -------------------------------------------------------

    TUN4 EQU H'0004'
    TUN3 EQU H'0003'
    TUN2 EQU H'0002'
    TUN1 EQU H'0001'
    TUN0 EQU H'0000'

    ;----- ANSEL
    --------------------------------------------------------------

    ANS7 EQU H'0007'
    ANS6 EQU H'0006'
    ANS5 EQU H'0005'
    ANS4 EQU H'0004'
    ANS3 EQU H'0003'
    ANS2 EQU H'0002'
    ANS1 EQU H'0001'
    ANS0 EQU H'0000'

    ;----- IOC
    --------------------------------------------------------------

    IOC5 EQU H'0005'
    IOC4 EQU H'0004'
    IOC3 EQU H'0003'
    IOC2 EQU H'0002'
    IOC1 EQU H'0001'
    IOC0 EQU H'0000'

    ;----- IOCA
    --------------------------------------------------------------

    IOCA5 EQU H'0005'
    IOCA4 EQU H'0004'
    IOCA3 EQU H'0003'
    IOCA2 EQU H'0002'
    IOCA1 EQU H'0001'
    IOCA0 EQU H'0000'

    ;----- VRCON Bits
    ---------------------------------------------------------

    VREN EQU H'0007'
    VRR EQU H'0005'
    VR3 EQU H'0003'
    VR2 EQU H'0002'
    VR1 EQU H'0001'
    VR0 EQU H'0000'

    ;----- EECON1
    -------------------------------------------------------------

    WRERR EQU H'0003'
    WREN EQU H'0002'
    WR EQU H'0001'
    RD EQU H'0000'

    ;----- ADCON1
    -------------------------------------------------------------

    ADCS2 EQU H'0006'
    ADCS1 EQU H'0005'
    ADCS0 EQU H'0004'

    ;==========================================================================
    ;
    ; RAM Definition
    ;
    ;==========================================================================

    __MAXRAM H'FF'
    __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
    __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94',
    H'97'-H'98', H'C0'-H'EF'

    ;==========================================================================
    ;
    ; Configuration Bits
    ;
    ;==========================================================================

    _FCMEN_ON EQU H'3FFF'
    _FCMEN_OFF EQU H'37FF'
    _IESO_ON EQU H'3FFF'
    _IESO_OFF EQU H'3BFF'
    _BOD_ON EQU H'3FFF'
    _BOD_NSLEEP EQU H'3EFF'
    _BOD_SBODEN EQU H'3DFF'
    _BOD_OFF EQU H'3CFF'
    _CPD_ON EQU H'3F7F'
    _CPD_OFF EQU H'3FFF'
    _CP_ON EQU H'3FBF'
    _CP_OFF EQU H'3FFF'
    _MCLRE_ON EQU H'3FFF'
    _MCLRE_OFF EQU H'3FDF'
    _PWRTE_OFF EQU H'3FFF'
    _PWRTE_ON EQU H'3FEF'
    _WDT_ON EQU H'3FFF'
    _WDT_OFF EQU H'3FF7'
    _LP_OSC EQU H'3FF8'
    _XT_OSC EQU H'3FF9'
    _HS_OSC EQU H'3FFA'
    _EC_OSC EQU H'3FFB'
    _INTRC_OSC_NOCLKOUT EQU H'3FFC'
    _INTRC_OSC_CLKOUT EQU H'3FFD'
    _EXTRC_OSC_NOCLKOUT EQU H'3FFE'
    _EXTRC_OSC_CLKOUT EQU H'3FFF'
    _INTOSCIO EQU H'3FFC'
    _INTOSC EQU H'3FFD'
    _EXTRCIO EQU H'3FFE'
    _EXTRC EQU H'3FFF'

    LIST

     
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    user_id=884387

    The resultant pic16f684.h that gets created from
    p16f684.inc, using the perl script (for convenience only):

    //
    // Register Declarations for Microchip 16F684 Processor
    //
    //
    // This header file was automatically generated by:
    //
    // inc2h.pl V1.5
    //
    // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
    //
    // SDCC is licensed under the GNU Public license (GPL) v2.
    Note that
    // this license covers the code to the compiler and other
    executables,
    // but explicitly does not cover any code or objects
    generated by sdcc.
    // We have not yet decided on a license for the run time
    libraries, but
    // it will not put any requirements on code linked against
    it. See:
    //
    // http://www.gnu.org/copyleft/gpl/html
    //
    // See http://sdcc.sourceforge.net/ for the latest
    information on sdcc.
    //
    //
    #ifndef P16F684_H
    #define P16F684_H

    #ifndef BIT_AT
    #define BIT_AT(base,bitno) sbit at ((base<<3)+bitno)
    #endif

    //
    // Register addresses.
    //
    #define INDF_ADDR 0x0000
    #define TMR0_ADDR 0x0001
    #define PCL_ADDR 0x0002
    #define STATUS_ADDR 0x0003
    #define FSR_ADDR 0x0004
    #define PORTA_ADDR 0x0005
    #define PORTC_ADDR 0x0007
    #define PCLATH_ADDR 0x000A
    #define INTCON_ADDR 0x000B
    #define PIR1_ADDR 0x000C
    #define TMR1L_ADDR 0x000E
    #define TMR1H_ADDR 0x000F
    #define T1CON_ADDR 0x0010
    #define TMR2_ADDR 0x0011
    #define T2CON_ADDR 0x0012
    #define CCPR1L_ADDR 0x0013
    #define CCPR1H_ADDR 0x0014
    #define CCP1CON_ADDR 0x0015
    #define PWM1CON_ADDR 0x0016
    #define ECCPAS_ADDR 0x0017
    #define WDTCON_ADDR 0x0018
    #define CMCON0_ADDR 0x0019
    #define CMCON1_ADDR 0x001A
    #define ADRESH_ADDR 0x001E
    #define ADCON0_ADDR 0x001F
    #define OPTION_REG_ADDR 0x0081
    #define TRISA_ADDR 0x0085
    #define TRISC_ADDR 0x0087
    #define PIE1_ADDR 0x008C
    #define PCON_ADDR 0x008E
    #define OSCCON_ADDR 0x008F
    #define OSCTUNE_ADDR 0x0090
    #define ANSEL_ADDR 0x0091
    #define PR2_ADDR 0x0092
    #define WPU_ADDR 0x0095
    #define WPUA_ADDR 0x0095
    #define IOC_ADDR 0x0096
    #define IOCA_ADDR 0x0096
    #define VRCON_ADDR 0x0099
    #define EEDAT_ADDR 0x009A
    #define EEDATA_ADDR 0x009A
    #define EEADR_ADDR 0x009B
    #define EECON1_ADDR 0x009C
    #define EECON2_ADDR 0x009D
    #define ADRESL_ADDR 0x009E
    #define ADCON1_ADDR 0x009F

    //
    // Memory organization.
    //
    #pragma maxram 0xFF

    #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
    #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
    #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
    #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
    #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
    #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
    #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
    #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
    #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
    #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
    #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
    #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
    #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
    #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
    #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
    #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
    #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
    #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
    #pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON
    #pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS
    #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
    #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
    #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
    #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
    #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
    #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 //
    OPTION_REG
    #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
    #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
    #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
    #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
    #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
    #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
    #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
    #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
    #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
    #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
    #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
    #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
    #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
    #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
    #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
    #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
    #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
    #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
    #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
    #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1

    // LIST
    // P16F684.INC Standard Header File, Version 1.03
    Microchip Technology, Inc.
    // NOLIST

    // This header file defines configurations, registers, and
    other useful bits of
    // information for the PIC16F684 microcontroller. These
    names are taken to match
    // the data sheets as closely as possible.

    // Note that the processor must be selected before this file is
    // included. The processor may be selected the following ways:

    // 1. Command line switch:
    // C:\ MPASM MYFILE.ASM /PIC16F684
    // 2. LIST directive in the source file
    // LIST P=PIC16F684
    // 3. Processor Type entry in the MPASM full-screen
    interface

    //==========================================================================
    //
    // Revision History
    //
    //==========================================================================
    //1.00 03/20/03 Original
    //1.01 08/04/03 Updated CMCON1 address
    //1.02 08/05/03 Updated names to match datasheet
    //1.03 08/11/03 Updated ULPWUE bit name to match datasheet
    //1.04 12/28/05 Updated COMCON* reference in comments to CMCON*
    //==========================================================================
    //
    // Verify Processor
    //
    //==========================================================================

    // IFNDEF __16F684
    // MESSG "Processor-header file mismatch. Verify
    selected processor."
    // ENDIF

    //==========================================================================
    //
    // Register Definitions
    //
    //==========================================================================

    #define W 0x0000
    #define F 0x0001

    //----- Register
    Files------------------------------------------------------

    data at INDF_ADDR volatile char INDF;
    sfr at TMR0_ADDR TMR0;
    data at PCL_ADDR volatile char PCL;
    sfr at STATUS_ADDR STATUS;
    sfr at FSR_ADDR FSR;
    sfr at PORTA_ADDR PORTA;

    sfr at PORTC_ADDR PORTC;

    sfr at PCLATH_ADDR PCLATH;
    sfr at INTCON_ADDR INTCON;
    sfr at PIR1_ADDR PIR1;

    sfr at TMR1L_ADDR TMR1L;
    sfr at TMR1H_ADDR TMR1H;
    sfr at T1CON_ADDR T1CON;
    sfr at TMR2_ADDR TMR2;
    sfr at T2CON_ADDR T2CON;
    sfr at CCPR1L_ADDR CCPR1L;
    sfr at CCPR1H_ADDR CCPR1H;
    sfr at CCP1CON_ADDR CCP1CON;
    sfr at PWM1CON_ADDR PWM1CON;
    sfr at ECCPAS_ADDR ECCPAS;
    sfr at WDTCON_ADDR WDTCON;
    sfr at CMCON0_ADDR CMCON0;
    sfr at CMCON1_ADDR CMCON1;

    sfr at ADRESH_ADDR ADRESH;
    sfr at ADCON0_ADDR ADCON0;

    sfr at OPTION_REG_ADDR OPTION_REG;

    sfr at TRISA_ADDR TRISA;
    sfr at TRISC_ADDR TRISC;

    sfr at PIE1_ADDR PIE1;

    sfr at PCON_ADDR PCON;
    sfr at OSCCON_ADDR OSCCON;
    sfr at OSCTUNE_ADDR OSCTUNE;
    sfr at ANSEL_ADDR ANSEL;
    sfr at PR2_ADDR PR2;

    sfr at WPU_ADDR WPU;
    sfr at WPUA_ADDR WPUA;
    sfr at IOC_ADDR IOC;
    sfr at IOCA_ADDR IOCA;

    sfr at VRCON_ADDR VRCON;
    sfr at EEDAT_ADDR EEDAT;
    sfr at EEDATA_ADDR EEDATA;
    sfr at EEADR_ADDR EEADR;
    sfr at EECON1_ADDR EECON1;
    sfr at EECON2_ADDR EECON2;
    sfr at ADRESL_ADDR ADRESL;
    sfr at ADCON1_ADDR ADCON1;

    //----- STATUS Bits
    --------------------------------------------------------

    BIT_AT(STATUS_ADDR,7) IRP;
    BIT_AT(STATUS_ADDR,6) RP1;
    BIT_AT(STATUS_ADDR,5) RP0;
    BIT_AT(STATUS_ADDR,4) NOT_TO;
    BIT_AT(STATUS_ADDR,3) NOT_PD;
    BIT_AT(STATUS_ADDR,2) Z;
    BIT_AT(STATUS_ADDR,1) DC;
    BIT_AT(STATUS_ADDR,0) C;

    //----- INTCON Bits
    --------------------------------------------------------

    BIT_AT(INTCON_ADDR,7) GIE;
    BIT_AT(INTCON_ADDR,6) PEIE;
    BIT_AT(INTCON_ADDR,5) T0IE;
    BIT_AT(INTCON_ADDR,4) INTE;
    BIT_AT(INTCON_ADDR,3) RAIE;
    BIT_AT(INTCON_ADDR,2) T0IF;
    BIT_AT(INTCON_ADDR,1) INTF;
    BIT_AT(INTCON_ADDR,0) RAIF;

    //----- PIR1 Bits
    ----------------------------------------------------------

    BIT_AT(PIR1_ADDR,7) EEIF;
    BIT_AT(PIR1_ADDR,6) ADIF;
    BIT_AT(PIR1_ADDR,5) CCP1IF;
    BIT_AT(PIR1_ADDR,4) C2IF;
    BIT_AT(PIR1_ADDR,3) C1IF;
    BIT_AT(PIR1_ADDR,2) OSFIF;
    BIT_AT(PIR1_ADDR,1) T2IF;
    BIT_AT(PIR1_ADDR,1) TMR2IF;
    BIT_AT(PIR1_ADDR,0) T1IF;
    BIT_AT(PIR1_ADDR,0) TMR1IF;

    //----- T1CON Bits
    ---------------------------------------------------------

    BIT_AT(T1CON_ADDR,7) T1GINV;
    BIT_AT(T1CON_ADDR,6) TMR1GE;
    BIT_AT(T1CON_ADDR,5) T1CKPS1;
    BIT_AT(T1CON_ADDR,4) T1CKPS0;
    BIT_AT(T1CON_ADDR,3) T1OSCEN;
    BIT_AT(T1CON_ADDR,2) NOT_T1SYNC;
    BIT_AT(T1CON_ADDR,1) TMR1CS;
    BIT_AT(T1CON_ADDR,0) TMR1ON;

    //----- T2CON Bits
    ---------------------------------------------------------

    BIT_AT(T2CON_ADDR,6) TOUTPS3;
    BIT_AT(T2CON_ADDR,5) TOUTPS2;
    BIT_AT(T2CON_ADDR,4) TOUTPS1;
    BIT_AT(T2CON_ADDR,3) TOUTPS0;
    BIT_AT(T2CON_ADDR,2) TMR2ON;
    BIT_AT(T2CON_ADDR,1) T2CKPS1;
    BIT_AT(T2CON_ADDR,0) T2CKPS0;

    //----- CCP1CON Bits
    -------------------------------------------------------

    BIT_AT(CCP1CON_ADDR,7) P1M1;
    BIT_AT(CCP1CON_ADDR,6) P1M0;
    BIT_AT(CCP1CON_ADDR,5) DC1B1;
    BIT_AT(CCP1CON_ADDR,4) DC1B0;
    BIT_AT(CCP1CON_ADDR,3) CCP1M3;
    BIT_AT(CCP1CON_ADDR,2) CCP1M2;
    BIT_AT(CCP1CON_ADDR,1) CCP1M1;
    BIT_AT(CCP1CON_ADDR,0) CCP1M0;

    //----- PWM1CON Bits
    -------------------------------------------------------

    BIT_AT(PWM1CON_ADDR,7) PRSEN;
    BIT_AT(PWM1CON_ADDR,6) PDC6;
    BIT_AT(PWM1CON_ADDR,5) PDC5;
    BIT_AT(PWM1CON_ADDR,4) PDC4;
    BIT_AT(PWM1CON_ADDR,3) PDC3;
    BIT_AT(PWM1CON_ADDR,2) PDC2;
    BIT_AT(PWM1CON_ADDR,1) PDC1;
    BIT_AT(PWM1CON_ADDR,0) PDC0;

    //----- ECCPAS Bits
    --------------------------------------------------------

    BIT_AT(ECCPAS_ADDR,7) ECCPASE;
    BIT_AT(ECCPAS_ADDR,6) ECCPAS2;
    BIT_AT(ECCPAS_ADDR,5) ECCPAS1;
    BIT_AT(ECCPAS_ADDR,4) ECCPAS0;
    BIT_AT(ECCPAS_ADDR,3) PSSAC1;
    BIT_AT(ECCPAS_ADDR,2) PSSAC0;
    BIT_AT(ECCPAS_ADDR,1) PSSBD1;
    BIT_AT(ECCPAS_ADDR,0) PSSBD0;

    //----- WDTCON Bits
    --------------------------------------------------------

    BIT_AT(WDTCON_ADDR,4) WDTPS3;
    BIT_AT(WDTCON_ADDR,3) WDTPS2;
    BIT_AT(WDTCON_ADDR,2) WDTPS1;
    BIT_AT(WDTCON_ADDR,1) WDTPS0;
    BIT_AT(WDTCON_ADDR,0) SWDTEN;

    //----- CMCON0 Bits
    -------------------------------------------------------

    BIT_AT(CMCON0_ADDR,7) C2OUT;
    BIT_AT(CMCON0_ADDR,6) C1OUT;
    BIT_AT(CMCON0_ADDR,5) C2INV;
    BIT_AT(CMCON0_ADDR,4) C1INV;
    BIT_AT(CMCON0_ADDR,3) CIS;
    BIT_AT(CMCON0_ADDR,2) CM2;
    BIT_AT(CMCON0_ADDR,1) CM1;
    BIT_AT(CMCON0_ADDR,0) CM0;

    //----- CMCON1 Bits
    -------------------------------------------------------

    BIT_AT(CMCON1_ADDR,1) T1GSS;
    BIT_AT(CMCON1_ADDR,0) C2SYNC;

    //----- ADCON0 Bits
    --------------------------------------------------------

    BIT_AT(ADCON0_ADDR,7) ADFM;
    BIT_AT(ADCON0_ADDR,6) VCFG;
    BIT_AT(ADCON0_ADDR,4) CHS2;
    BIT_AT(ADCON0_ADDR,3) CHS1;
    BIT_AT(ADCON0_ADDR,2) CHS0;
    BIT_AT(ADCON0_ADDR,1) GO;
    BIT_AT(ADCON0_ADDR,1) NOT_DONE;
    BIT_AT(ADCON0_ADDR,1) GO_DONE;
    BIT_AT(ADCON0_ADDR,0) ADON;

    //----- OPTION Bits
    --------------------------------------------------------

    BIT_AT(OPTION_REG_ADDR,7) NOT_RAPU;
    BIT_AT(OPTION_REG_ADDR,6) INTEDG;
    BIT_AT(OPTION_REG_ADDR,5) T0CS;
    BIT_AT(OPTION_REG_ADDR,4) T0SE;
    BIT_AT(OPTION_REG_ADDR,3) PSA;
    BIT_AT(OPTION_REG_ADDR,2) PS2;
    BIT_AT(OPTION_REG_ADDR,1) PS1;
    BIT_AT(OPTION_REG_ADDR,0) PS0;

    //----- PIE1 Bits
    ----------------------------------------------------------

    BIT_AT(PIE1_ADDR,7) EEIE;
    BIT_AT(PIE1_ADDR,6) ADIE;
    BIT_AT(PIE1_ADDR,5) CCP1IE;
    BIT_AT(PIE1_ADDR,4) C2IE;
    BIT_AT(PIE1_ADDR,3) C1IE;
    BIT_AT(PIE1_ADDR,2) OSFIE;
    BIT_AT(PIE1_ADDR,1) T2IE;
    BIT_AT(PIE1_ADDR,1) TMR2IE;
    BIT_AT(PIE1_ADDR,0) T1IE;
    BIT_AT(PIE1_ADDR,0) TMR1IE;

    //----- PCON Bits
    ----------------------------------------------------------

    BIT_AT(PCON_ADDR,5) ULPWUE;
    BIT_AT(PCON_ADDR,4) SBODEN;
    BIT_AT(PCON_ADDR,1) NOT_POR;
    BIT_AT(PCON_ADDR,0) NOT_BOD;

    //----- OSCCON Bits
    --------------------------------------------------------

    BIT_AT(OSCCON_ADDR,6) IRCF2;
    BIT_AT(OSCCON_ADDR,5) IRCF1;
    BIT_AT(OSCCON_ADDR,4) IRCF0;
    BIT_AT(OSCCON_ADDR,3) OSTS;
    BIT_AT(OSCCON_ADDR,2) HTS;
    BIT_AT(OSCCON_ADDR,1) LTS;
    BIT_AT(OSCCON_ADDR,0) SCS;

    //----- OSCTUNE Bits
    -------------------------------------------------------

    BIT_AT(OSCTUNE_ADDR,4) TUN4;
    BIT_AT(OSCTUNE_ADDR,3) TUN3;
    BIT_AT(OSCTUNE_ADDR,2) TUN2;
    BIT_AT(OSCTUNE_ADDR,1) TUN1;
    BIT_AT(OSCTUNE_ADDR,0) TUN0;

    //----- ANSEL
    --------------------------------------------------------------

    #define ANS7 0x0007
    #define ANS6 0x0006
    #define ANS5 0x0005
    #define ANS4 0x0004
    #define ANS3 0x0003
    #define ANS2 0x0002
    #define ANS1 0x0001
    #define ANS0 0x0000

    //----- IOC
    --------------------------------------------------------------

    #define IOC5 0x0005
    #define IOC4 0x0004
    #define IOC3 0x0003
    #define IOC2 0x0002
    #define IOC1 0x0001
    #define IOC0 0x0000

    //----- IOCA
    --------------------------------------------------------------

    #define IOCA5 0x0005
    #define IOCA4 0x0004
    #define IOCA3 0x0003
    #define IOCA2 0x0002
    #define IOCA1 0x0001
    #define IOCA0 0x0000

    //----- VRCON Bits
    ---------------------------------------------------------

    BIT_AT(VRCON_ADDR,7) VREN;
    BIT_AT(VRCON_ADDR,5) VRR;
    BIT_AT(VRCON_ADDR,3) VR3;
    BIT_AT(VRCON_ADDR,2) VR2;
    BIT_AT(VRCON_ADDR,1) VR1;
    BIT_AT(VRCON_ADDR,0) VR0;

    //----- EECON1
    -------------------------------------------------------------

    #define WRERR 0x0003
    #define WREN 0x0002
    #define WR 0x0001
    #define RD 0x0000

    //----- ADCON1
    -------------------------------------------------------------

    #define ADCS2 0x0006
    #define ADCS1 0x0005
    #define ADCS0 0x0004

    //==========================================================================
    //
    // RAM Definition
    //
    //==========================================================================

    // __MAXRAM H'FF'
    // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
    // __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94',
    H'97'-H'98', H'C0'-H'EF'

    //==========================================================================
    //
    // Configuration Bits
    //
    //==========================================================================

    #define _FCMEN_ON 0x3FFF
    #define _FCMEN_OFF 0x37FF
    #define _IESO_ON 0x3FFF
    #define _IESO_OFF 0x3BFF
    #define _BOD_ON 0x3FFF
    #define _BOD_NSLEEP 0x3EFF
    #define _BOD_SBODEN 0x3DFF
    #define _BOD_OFF 0x3CFF
    #define _CPD_ON 0x3F7F
    #define _CPD_OFF 0x3FFF
    #define _CP_ON 0x3FBF
    #define _CP_OFF 0x3FFF
    #define _MCLRE_ON 0x3FFF
    #define _MCLRE_OFF 0x3FDF
    #define _PWRTE_OFF 0x3FFF
    #define _PWRTE_ON 0x3FEF
    #define _WDT_ON 0x3FFF
    #define _WDT_OFF 0x3FF7
    #define _LP_OSC 0x3FF8
    #define _XT_OSC 0x3FF9
    #define _HS_OSC 0x3FFA
    #define _EC_OSC 0x3FFB
    #define _INTRC_OSC_NOCLKOUT 0x3FFC
    #define _INTRC_OSC_CLKOUT 0x3FFD
    #define _EXTRC_OSC_NOCLKOUT 0x3FFE
    #define _EXTRC_OSC_CLKOUT 0x3FFF
    #define _INTOSCIO 0x3FFC
    #define _INTOSC 0x3FFD
    #define _EXTRCIO 0x3FFE
    #define _EXTRC 0x3FFF

    // LIST
    #endif

     
  • Logged In: YES
    user_id=884387

    The required picp changes for 16F684 support (determined
    using the companion program that comes with picp: picsnoop)

    //-----------------------------------------------------------
    const static unsigned char def_PIC16F684[] =
    {
    0x08, 0x00, // size of program space
    0x3f, 0xff, // width of address word
    0x3f, 0xff, // width of data word
    0x00, 0x7f, // width of ID
    0x00, 0x7f, // ID mask
    0x0f, 0xff, // width of configuration word
    0x0f, 0xff, // configuration word mask
    0x00, 0xff, // EEPROM data width
    0x00, 0xff, // EEPROM data mask
    0x00, 0x00, // Calibration width
    0x00, 0x00, // Calibration mask
    0x00, 0x00, // ??
    0x08, 0x00, // ??
    0x20, 0x00, // address of ID locations
    0x04, // size of ID locations
    0x20, 0x07, // address of configuration bits
    0x01, // size of configuration register
    0x00, 0x00, // address of data space
    0x01, 0x00, // size of data space
    0x00, 0x00, // address of internal clock calibration value
    0x00, 0x00, // size of clock calibration space
    0x00, // additional programming pulses for C devices
    0x01, // main programming pulses for C devices
    0x15, 0x0f, // ZIF configuration ??
    };

    const static unsigned char defx_PIC16F684[] =
    {
    0x0f, 0xff, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00,
    0x0f, 0xff, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00,
    0x00, 0x00, 0x00, 0x00,
    };

    const static PIC_DEFINITION PIC16F684 =
    {
    "PIC16F684", // device name
    def_PIC16F684, // definition
    defx_PIC16F684, // extended definition
    0, // config word: code protect bit mask
    0, // config word: watchdog bit mask

    0, // Word alignment for writing to this device
    0, // Configuration memory start address
    0, 0, // ID Locations addr
    0, // Data eeprom address
    0, // number of words in cfg bits with factory set bits
    {0, 0, 0, 0, 0, 0, 0, 0}, // fixed bits mask
    (P_PICSTART | P_WARP13 | P_JUPIC), // bit map of supporting
    programmers
    };

     
  • Maarten Brock
    Maarten Brock
    2006-04-07

    • status: open --> closed-out-of-date
     
  • Maarten Brock
    Maarten Brock
    2006-04-07

    Logged In: YES
    user_id=888171

    Pic16f684 and all other pic14's are now supported thanks to
    patch 1446111 by Zik Saleeba.