While reading the codegeneration functions in the PIC16
for various shift operations, I found one bug and a few
gen.c:8084 had a wrong literal 0xF0 instead of 0x0F
This would create wrong results for
i << 5 with an int i.
gen.c:8218 reads the sign bit after some rotations from
place. Bit 15 from the left operand is only once
This would cause "i >> 6" to fail for signed ints
i, but the
compiler does not erach this point (see my bugreport
Minor improvements are:
gen.c:7728ff one instruction can be saved by replacing two
RLCFW by one RLNCWF as the carry bit is ignored
gen.c:7744ff (same thing)
gen.c:7858ff one instruction can be saved by not
carry bit explicitly but replacing RRCF by RRNCF and
clearing bit 0 in the AND instruction above
Later (in case 6:) another instruction can be
replacing RLCF with RLNCF and thus keeping the carry
bit in the register (also have to modify the AND
The if-statements (size >= something) allowed for
beyond the size of the result operand (via the MOVWF
instructions with MSBxx+offr) --- though these cases
would only occur for queer result sizes (e.g. 3).
Patch to be applied in src/pic16 with -p0.
BTW: These routines have certainly been a good deal of
work, thank you for your engagement!