I installed the SDCC c compiler for use with SiLabs 8051 micro about a month ago. I finished my application but in the process I've also branched some of the code off and written a faster 32-bit floating division routine for most any 8051 core device. It follows the special case and error handling of the existing library routine, so it shouldn't break anything there. Roughly speaking, it is about twice as fast as the ___fsdiv.c file I found in sdcc\lib\src, based on the assembly version and not the generic GNU c code for it. It's a non-restoring division version, with 4 unrolled bits generated per loop. It is well-documented in the source file, as well. Extremely well documented.
Yes, it's larger. No, although I think it is well crafted, it is not well tested as yet and I've not walked it through a code review with anyone. Like the existing library, it does not do much more with denormals than recognize them as effectively zero. I didn't want to break anything by adding better denormal handling. Like the existing routine, it does not preserve sign when INF or NaN is generated. Again, not wanting to break things that may already depend on existing behavior.
Not sure how to contribute it, but I'm willing to consider doing that if it may be wanted. If not, that's fine. I can post it up on my web site.
PS. I do NOT come here often and I'm not sure when I next may do so. I can be contacted directly at email@example.com.