From: M O Altmann <m.altmann@fc...> - 2004-07-28 10:50:58
I'm starting to get the hang of how things work (in general) within
architecture specific ralloc.c/h and gen.c/h. By comparing each port
with another I realised that there are very different approaches to
eg. register allocation (ralloc).
The PicoBlaze architecture has 16 Bytes of general purpose
registers (GPR) plus 64 Bytes of "scratch pad" (luxurious ?!) but no
hardware stack. GPR can be used to either store data or addresses
(which point to a mem location in the scratch pad). The scratch pad
registers cannot be accessed directly but instead are (a) read by
copying the contents to a GPR, using FETCH and (b) modified by
copying data from a GPR, using STORE.
example (from pg.48 of user guide UG129.pdf) with added comments:
> NAMEREG s0, ram_data ; like "#define"
> NAMEREG s1, ram_address
> CONSTANT ram_locations, 40 ; (HEX!) there are 64 locations
> CONSTANT initial_value, 00 ; initialize to zero
> LOAD ram_data, initial_value ; load GPR to be written
> LOAD ram_address, ram_locations ; load GPR containg address
> ram_fill: ; fill from top to bottom
> SUB ram_address, 01 ; ...decrement address
> STORE ram_data, (ram_address); initialize location
> JUMP NZ, ram_fill ; if not address 0,
> ; goto ram_fill
It is clear, that the scratch pad is ideal for implementing one (or
more) stack(s). The question is whether to allocate a set number of
scratch Bytes as stack or to dynamically allocate memory for a stack.
Further more I haven't found a place to define carry/zero/status
bits. Maybe someone can point me into the right direction?
I am sure you (developers of ports) have had previous discussions on
how to make best use of a particular architecture and would welcome
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