From: Stephen M. Kenton <skenton@ou...> - 2001-12-11 05:46:41
I've been following sdcc off/on for a couple
of years, but am only now able to try coding
again. I'm now hacking on a local copy and
would appreciate some feedback.
I have been examining register bank handling in
the MCS-51 port. Except for the case of an ISR,
if someone really wants to make inter-bank calls
(i.e. different USING in caller and callee) It
looks to me like the compiler logic could be
made much simpler by having the caller change
register banks by setting the psw in gencall/genpcall
immediately before the lcall and restore them
immediatly after the return. This way, the entry
code would not have to set the bank on entry each
time etc. which would make routines compiled for
using register bank 0 and those compiled using
non-zero register banks generate similar code.
I don't see any value to having check for zero and
non-zero register bank which are handled differently.
Sandeep, this would not play well with the idea of
pseudo registers since there is not internal ram
to have pseudo registers for all 4 banks, I expect.
For the case of an ISR which must push and modify
the psw to use a different register bank, gencall
could omit the bank change and just treat it like
a call to a normal function where both the caller
and callee use the same register bank because the
ISR entry/exit linkage would allow it to be called
for testing/debug purposes. Only if the ISR used
the same register bank as the caller would it need
to save registers other than the psw on entry.
This is the whole purpose of multiple register
banks on the 8051, low latency interrupt handling.
Given the very limited stack, it's probably not a
good idea to use the same register bank for the
"normal" and ISR routines anyway.