[sdcc-devel] [ sdcc-Bugs-1057979 ] atoi/atol fail on builds after Feb 23 2004

[SourceForge.net <no...@so...>]

Bugs item #1057979, was opened at 2004-10-31 21:24
Message generated for change (Comment added) made by davija
You can respond by visiting: 
https://sourceforge.net/tracker/?func=detail&atid=100599&aid=1057979&group_id=599

Category: None
Group: None
Status: Open
Resolution: None
Priority: 5
Submitted By: James Davis (davija)
Assigned to: Nobody/Anonymous (nobody)
Summary: atoi/atol fail on builds after Feb 23 2004

Initial Comment:
I recently upgraded from:
SDCC : 
mcs51/gbz80/z80/avr/ds390/pic16/pic14/TININative/xa51
/ds400/hc08 2.4.0 (Feb 23 2004) (MINGW32)

to version:
SDCC : 
mcs51/gbz80/z80/avr/ds390/pic16/pic14/TININative/xa51
/ds400/hc08 2.4.6 #872 (Oct 28 2004) (MINGW32)

In the original Feb 23 release, my original code compiles 
and runs correctly (except some issues with certain 
variables fixed by newer version).  atoi and atol function 
as expected.

after the upgrade, the atoi and atol functions do not 
provide correct output for values greater than 99. (I 
also wrote my own simplified version of these to the 
same result).

When I run the code attached below in any version after 
Feb 23, the result is :101:
in Feb 23, the result is :100:
the command line arugments that my IDE uses is:
-c --debug --use-stdout -V 

also, other results 
atoi(1000) = 1010
atoi(>2000) = 2020
some values also include 1919.
they are always in repitition as seen.  on some larger 
values, the 2 digits are repeated more times. (ex. 
42424242)

Here is some bare-bones code that shows the issue.

-- main.c ---
#include "c8051f120.h"
#include "uart.h"
#include "config.h"
#include <stdio.h>
#include <stdlib.h>

void main()
{
  Init_Device();
  printf(":%d:\r\n",atoi("100"));
  while(1)
  {
  }
}

void UART_ISR(void) interrupt 4
{
  char tmp;
  char SFR_PAGE = SFRPAGE;
  SFRPAGE=UART0_PAGE;
  ES0=0;
  // If it's time to transmit...
  if (TI0==1)
  {
    // Clear flag
    TI0=0;
  }

  // If a char came in
  if (RI0==1)
  {
    // if the queue is not full
    if (!RX_Full())

    // Buffer the char -- otherwise drop it.
      addRX(SBUF0);   

    if (UART_LE)
	{
      tmp=SBUF0;
  	  SBUF0=tmp;
  	  while(TI0==0);
   	  TI0=0;
    }
    
	// clear recv flag
    RI0=0;
  }
  ES0=1;
  SFRPAGE=SFR_PAGE;
}

-- config.c --
/////////////////////////////////////
// Config2 Code Configuration File //
/////////////////////////////////////

#include "c8051F120.h"
#include "config.h"
#include "uart.h"

// Peripheral specific initialization functions,
// Called from the Init_Device() function
void Reset_Sources_Init()
{
    WDTCN     = 0xDE;
    WDTCN     = 0xAD;
    SFRPAGE   = LEGACY_PAGE;
    RSTSRC    = 0x04;
}

void Port_IO_Init()
{
    // P0.0  -  TX0 (UART0), Push-Pull,  Digital
    // P0.1  -  RX0 (UART0), Open-Drain, Digital
    // P0.2  -  Unassigned,  Push-Pull,  Digital
    // P0.3  -  Unassigned,  Push-Pull,  Digital
    // P0.4  -  Unassigned,  Push-Pull,  Digital
    // P0.5  -  Unassigned,  Push-Pull,  Digital
    // P0.6  -  Unassigned,  Push-Pull,  Digital
    // P0.7  -  Unassigned,  Push-Pull,  Digital

    // P1.0  -  Unassigned,  Push-Pull,  Digital
    // P1.1  -  Unassigned,  Push-Pull,  Digital
    // P1.2  -  Unassigned,  Push-Pull,  Digital
    // P1.3  -  Unassigned,  Push-Pull,  Digital
    // P1.4  -  Unassigned,  Push-Pull,  Digital
    // P1.5  -  Unassigned,  Push-Pull,  Digital
    // P1.6  -  Unassigned,  Push-Pull,  Digital
    // P1.7  -  Unassigned,  Push-Pull,  Digital

    // P2.0  -  Unassigned,  Push-Pull,  Digital
    // P2.1  -  Unassigned,  Push-Pull,  Digital
    // P2.2  -  Unassigned,  Push-Pull,  Digital
    // P2.3  -  Unassigned,  Push-Pull,  Digital
    // P2.4  -  Unassigned,  Push-Pull,  Digital
    // P2.5  -  Unassigned,  Push-Pull,  Digital
    // P2.6  -  Unassigned,  Push-Pull,  Digital
    // P2.7  -  Unassigned,  Push-Pull,  Digital

    // P3.0  -  Unassigned,  Push-Pull,  Digital
    // P3.1  -  Unassigned,  Push-Pull,  Digital
    // P3.2  -  Unassigned,  Push-Pull,  Digital
    // P3.3  -  Unassigned,  Push-Pull,  Digital
    // P3.4  -  Unassigned,  Push-Pull,  Digital
    // P3.5  -  Unassigned,  Push-Pull,  Digital
    // P3.6  -  Unassigned,  Push-Pull,  Digital
    // P3.7  -  Unassigned,  Push-Pull,  Digital

    SFRPAGE   = CONFIG_PAGE;
    P0MDOUT   = 0xFD;
    P1MDOUT   = 0xFF;
    P2MDOUT   = 0xFF;
    P3MDOUT   = 0xFF;
    P4MDOUT   = 0xFF;
    P5MDOUT   = 0xFF;
    P6MDOUT   = 0xFF;
    P7MDOUT   = 0xFF;
    XBR0      = 0x04;
	XBR1	  = 0x00;
    XBR2      = 0x40;
}

void setport(int dir)
{
  char SFR_SAVE;
  SFR_SAVE = SFRPAGE;
  SFRPAGE = CONFIG_PAGE;
  if (dir==PORT_IN)
  {
    P5MDOUT = 0x00;
  	P7MDOUT = 0x00;
  	P4MDOUT = 0xFE;
  	P4_0=1;
    P5=0xFF;
    P7=0xFF;
  }
  else
  {
    P5MDOUT = 0xFF;
  	P7MDOUT = 0xFF;
  	P4MDOUT = 0xFF;
  }
  SFRPAGE = SFR_SAVE;
}

void Oscillator_Init()
{
  int i = 0;
  SFRPAGE   = CONFIG_PAGE;
  SFRPAGE   = LEGACY_PAGE;
  FLSCL     = 0xB0;
  SFRPAGE   = CONFIG_PAGE;
  PLL0CN    |= 0x01;
  PLL0DIV   = 0x01;
  PLL0FLT   = 0x01;
  PLL0MUL   = 0x04;
  for (i = 0; i < 15; i++);  // Wait 5us for initialization
  PLL0CN    |= 0x02;
  while ((PLL0CN & 0x10) == 0);
  CLKSEL    = 0x02;
  OSCICN    = 0x83;
}

void Timer_Init()
{
  SFRPAGE = TIMER01_PAGE;
  TMOD  = 0x20;
  CKCON = 0x10;
  TH1   = 0xCB;
//  TH1 = 0x60;
}

void UART_Init()
{
  SFRPAGE = UART0_PAGE;
  SCON0 = 0x50;
  SSTA0 |= 0x10;
  SFRPAGE = TIMER01_PAGE;
  TR1=1;
  SFRPAGE = UART0_PAGE;
  TI0=1;
  InitTX();
  InitRX();
}

void Interrupts_Init()
{
  IE = 0x90;
}

// Initialization function for device,
// Call Init_Device() from your main program
void Init_Device(void)
{
    Reset_Sources_Init();
    Port_IO_Init();
    Oscillator_Init();
    Timer_Init();
    UART_Init();
	Interrupts_Init();
}

-- config.h -- 
/////////////////////////////////////
// Config2 Code Configuration File //
/////////////////////////////////////
#ifndef __CONFIG_H
#define __CONFIG_H

#define BAUDRATE     9600              // Baud rate of 
UART in bps
#define INTCLK       24500000          // Internal 
oscillator frequency in Hz
#define SYSCLK       98000000          // Output of PLL 
derived from (INTCLK*4)
#define PORT_IN  0
#define PORT_OUT 1

void Reset_Sources_Init();
void Port_IO_Init();
void Oscillator_Init();
void Timer_Init();
void UART_Init();
void Init_Device();
void setport(int dir);

#endif
-- c8051f120.h --
/*----------------------------------------------------
-----------------------
;
;
;
;
; FILE NAME: C8051F120.H
; TARGET MCUs: C8051F120, F121, F122, F123, F124, 
F125, F126, F127
; DESCRIPTION: Register/bit definitions for the 
C8051F120 product family.
;
; REVISION 1.6
;
;------------------------------------------------------
---------------------*/

/*  BYTE Registers  */

sfr at 0x80 P0; /* PORT 0 LATCH */
sfr at 0x81 SP; /* STACK POINTER */
sfr at 0x82 DPL; /* DATA POINTER LOW BYTE */
sfr at 0x83 DPH; /* DATA POINTER HIGH BYTE */
sfr at 0x84 SFRPAGE; /* SFR PAGE SELECT */
sfr at 0x85 SFRNEXT; /* SFR STACK NEXT PAGE */
sfr at 0x86 SFRLAST; /* SFR STACK LAST PAGE */
sfr at 0x87 PCON; /* POWER CONTROL */
sfr at 0x88 FLSTAT; /* FLASH STATUS */
sfr at 0x88 CPT0CN; /* COMPARATOR 0 CONTROL */
sfr at 0x88 CPT1CN; /* COMPARATOR 1 CONTROL */
sfr at 0x88 TCON; /* TIMER/COUNTER CONTROL */
sfr at 0x89 TMOD; /* TIMER/COUNTER MODE */
sfr at 0x89 CPT0MD; /* COMPARATOR 0 CONFIGURATION 
*/
sfr at 0x89 CPT1MD; /* COMPARATOR 1 CONFIGURATION 
*/
sfr at 0x89 PLL0CN; /* PLL CONTROL */
sfr at 0x8A OSCICN; /* INTERNAL OSCILLATOR CONTROL 
*/
sfr at 0x8A TL0; /* TIMER/COUNTER 0 LOW BYTE */
sfr at 0x8B OSCICL; /* INTERNAL OSCILLATOR 
CALIBRATION */
sfr at 0x8B TL1; /* TIMER/COUNTER 1 LOW BYTE */
sfr at 0x8C OSCXCN; /* EXTERNAL OSCILLATOR 
CONTROL */
sfr at 0x8C TH0; /* TIMER/COUNTER 0 HIGH BYTE */
sfr at 0x8D TH1; /* TIMER/COUNTER 1 HIGH BYTE */
sfr at 0x8D PLL0DIV; /* PLL DIVIDER */
sfr at 0x8E CKCON; /* CLOCK CONTROL */
sfr at 0x8E PLL0MUL; /* PLL MULTIPLIER */
sfr at 0x8F PSCTL; /* FLASH WRITE/ERASE CONTROL */
sfr at 0x8F PLL0FLT; /* PLL FILTER */
sfr at 0x90 P1; /* PORT 1 LATCH */
sfr at 0x91 SSTA0; /* UART 0 STATUS */
sfr at 0x91 MAC0BL; /* MAC0 B REGISTER LOW BYTE */
sfr at 0x92 MAC0BH; /* MAC0 B REGISTER HIGH BYTE */
sfr at 0x93 MAC0ACC0; /* MAC0 ACCUMULATOR BYTE 0 
*/
sfr at 0x94 MAC0ACC1; /* MAC0 ACCUMULATOR BYTE 1 
*/
sfr at 0x95 MAC0ACC2; /* MAC0 ACCUMULATOR BYTE 2 
*/
sfr at 0x96 SFRPGCN; /* SFR PAGE CONTROL */
sfr at 0x96 MAC0ACC3; /* MAC0 ACCUMULATOR BYTE 3 
*/
sfr at 0x97 MAC0OVR; /* MAC0 ACCUMULATOR 
OVERFLOW BYTE */
sfr at 0x97 CLKSEL; /* SYSTEM CLOCK SELECT */
sfr at 0x98 SCON0; /* UART 0 CONTROL */
sfr at 0x98 SCON1; /* UART 1 CONTROL */
sfr at 0x99 SBUF0; /* UART 0 DATA BUFFER */
sfr at 0x99 SBUF1; /* UART 1 DATA BUFFER */
sfr at 0x9A SPI0CFG; /* SPI CONFIGURATION */
sfr at 0x9A CCH0MA; /* CACHE MISS ACCUMULATOR */
sfr at 0x9B SPI0DAT; /* SPI DATA */
sfr at 0x9C P4MDOUT; /* PORT 4 OUTPUT MODE 
CONFIGURATION */
sfr at 0x9D P5MDOUT; /* PORT 5 OUTPUT MODE 
CONFIGURATION */
sfr at 0x9D SPI0CKR; /* SPI CLOCK RATE CONTROL */
sfr at 0x9E P6MDOUT; /* PORT 6 OUTPUT MODE 
CONFIGURATION */
sfr at 0x9F P7MDOUT; /* PORT 7 OUTPUT MODE 
CONFIGURATION */
sfr at 0xA0 P2; /* PORT 2 LATCH */
sfr at 0xA1 EMI0TC; /* EMIF TIMING CONTROL */
sfr at 0xA1 CCH0CN; /* CACHE CONTROL */
sfr at 0xA2 EMI0CN; /* EMIF CONTROL */
sfr at 0xA2 CCH0TN; /* CACHE TUNING */
sfr at 0xA3 EMI0CF; /* EMIF CONFIGURATION */
sfr at 0xA3 CCH0LC; /* CACHE LOCK */
sfr at 0xA4 P0MDOUT; /* PORT 0 OUTPUT MODE 
CONFIGURATION */
sfr at 0xA5 P1MDOUT; /* PORT 1 OUTPUT MODE 
CONFIGURATION */
sfr at 0xA6 P2MDOUT; /* PORT 2 OUTPUT MODE 
CONFIGURATION */
sfr at 0xA7 P3MDOUT; /* PORT 3 OUTPUT MODE 
CONFIGURATION */
sfr at 0xA8 IE; /* INTERRUPT ENABLE */
sfr at 0xA9 SADDR0; /* UART 0 SLAVE ADDRESS */
sfr at 0xAD P1MDIN; /* PORT 1 INPUT MODE */
sfr at 0xB0 P3; /* PORT 3 LATCH */
sfr at 0xB1 PSBANK; /* FLASH BANK SELECT */
sfr at 0xB7 FLACL; /* FLASH ACCESS LIMIT */
sfr at 0xB7 FLSCL; /* FLASH SCALE */
sfr at 0xB8 IP; /* INTERRUPT PRIORITY */
sfr at 0xB9 SADEN0; /* UART 0 SLAVE ADDRESS MASK */
sfr at 0xBA AMX0CF; /* ADC0 MULTIPLEXER 
CONFIGURATION */
sfr at 0xBA AMX2CF; /* ADC2 MULTIPLEXER 
CONFIGURATION */
sfr at 0xBB AMX0SL; /* ADC0 MULTIPLEXER CHANNEL 
SELECT */
sfr at 0xBB AMX2SL; /* ADC2 MULTIPLEXER CHANNEL 
SELECT */
sfr at 0xBC ADC0CF; /* ADC0 CONFIGURATION */
sfr at 0xBC ADC2CF; /* ADC2 CONFIGURATION */
sfr at 0xBE ADC0L; /* ADC0 DATA WORD LOW BYTE */
sfr at 0xBE ADC2; /* ADC2DATA WORD */
sfr at 0xBF ADC0H; /* ADC0 DATA WORD HIGH BYTE */
sfr at 0xC0 MAC0STA; /* MAC0 STATUS */
sfr at 0xC0 SMB0CN; /* SMBUS CONTROL */
sfr at 0xC1 MAC0AL; /* MAC0 A REGISTER LOW BYTE */
sfr at 0xC1 SMB0STA; /* SMBUS STATUS */
sfr at 0xC2 MAC0AH; /* MAC0 A REGISTER HIGH BYTE */
sfr at 0xC2 SMB0DAT; /* SMBUS DATA */
sfr at 0xC3 MAC0CF; /* MAC0 CONFIGURATION 
REGISTER */
sfr at 0xC3 SMB0ADR; /* SMBUS SLAVE ADDRESS */
sfr at 0xC4 ADC0GTL; /* ADC0 GREATER-THAN LOW 
BYTE */
sfr at 0xC4 ADC2GT; /* ADC2 GREATER-THAN */
sfr at 0xC5 ADC0GTH; /* ADC0 GREATER-THAN HIGH 
BYTE */
sfr at 0xC6 ADC0LTL; /* ADC0 LESS-THAN LOW BYTE */
sfr at 0xC6 ADC2LT; /* ADC2 LESS-THAN */
sfr at 0xC7 ADC0LTH; /* ADC0 LESS-THAN HIGH BYTE */
sfr at 0xC8 P4; /* PORT 4 LATCH */
sfr at 0xC8 TMR2CN; /* TIMER/COUNTER 2 CONTROL */
sfr at 0xC8 TMR3CN; /* TIMER 3 CONTROL */
sfr at 0xC8 TMR4CN; /* TIMER/COUNTER 4 CONTROL */
sfr at 0xC9 TMR2CF; /* TIMER/COUNTER 2 
CONFIGURATION */
sfr at 0xC9 TMR3CF; /* TIMER 3 CONFIGURATION */
sfr at 0xC9 TMR4CF; /* TIMER/COUNTER 4 
CONFIGURATION */
sfr at 0xCA RCAP2L; /* TIMER/COUNTER 2 
CAPTURE/RELOAD LOW BYTE */
sfr at 0xCA RCAP3L; /* TIMER 3 CAPTURE/RELOAD LOW 
BYTE */
sfr at 0xCA RCAP4L; /* TIMER/COUNTER 4 
CAPTURE/RELOAD LOW BYTE */
sfr at 0xCB RCAP2H; /* TIMER/COUNTER 2 
CAPTURE/RELOAD HIGH BYTE */
sfr at 0xCB RCAP3H; /* TIMER 3 CAPTURE/RELOAD HIGH 
BYTE */
sfr at 0xCB RCAP4H; /* TIMER/COUNTER 4 
CAPTURE/RELOAD HIGH BYTE */
sfr at 0xCC TMR2L; /* TIMER/COUNTER 2 LOW BYTE */
sfr at 0xCC TMR3L; /* TIMER 3 LOW BYTE */
sfr at 0xCC TMR4L; /* TIMER/COUNTER 4 LOW BYTE */
sfr at 0xCD TMR2H; /* TIMER/COUNTER 2 HIGH BYTE */
sfr at 0xCD TMR3H; /* TIMER 3 HIGH BYTE */
sfr at 0xCD TMR4H; /* TIMER/COUNTER 4 HIGH BYTE */
sfr at 0xCE MAC0RNDL; /* MAC0 ROUNDING REGISTER 
LOW BYTE */
sfr at 0xCF MAC0RNDH; /* MAC0 ROUNDING REGISTER 
HIGH BYTE */
sfr at 0xCF SMB0CR; /* SMBUS CLOCK RATE */
sfr at 0xD0 PSW; /* PROGRAM STATUS WORD */
sfr at 0xD1 REF0CN; /* VOLTAGE REFERENCE CONTROL 
*/
sfr at 0xD2 DAC0L; /* DAC0 LOW BYTE */
sfr at 0xD2 DAC1L; /* DAC1 LOW BYTE */
sfr at 0xD3 DAC0H; /* DAC0 HIGH BYTE */
sfr at 0xD3 DAC1H; /* DAC1 HIGH BYTE */
sfr at 0xD4 DAC0CN; /* DAC0 CONTROL */
sfr at 0xD4 DAC1CN; /* DAC1 CONTROL */
sfr at 0xD8 P5; /* PORT 5 LATCH */
sfr at 0xD8 PCA0CN; /* PCA CONTROL */
sfr at 0xD9 PCA0MD; /* PCA MODE */
sfr at 0xDA PCA0CPM0; /* PCA MODULE 0 MODE */
sfr at 0xDB PCA0CPM1; /* PCA MODULE 1 MODE 
REGISTER */
sfr at 0xDC PCA0CPM2; /* PCA MODULE 2 MODE */
sfr at 0xDD PCA0CPM3; /* PCA MODULE 3 MODE */
sfr at 0xDE PCA0CPM4; /* PCA MODULE 4 MODE */
sfr at 0xDF PCA0CPM5; /* PCA MODULE 5 MODE */
sfr at 0xE0 ACC; /* ACCUMULATOR */
sfr at 0xE1 XBR0; /* PORT I/O CROSSBAR CONTROL 0 */
sfr at 0xE1 PCA0CPL5; /* PCA MODULE 5 
CAPTURE/COMPARE LOW BYTE */
sfr at 0xE2 PCA0CPH5; /* PCA MODULE 5 
CAPTURE/COMPARE HIGH BYTE */
sfr at 0xE2 XBR1; /* PORT I/O CROSSBAR CONTROL 1 */
sfr at 0xE3 XBR2; /* PORT I/O CROSSBAR CONTROL 2 */
sfr at 0xE6 EIE1; /* EXTENDED INTERRUPT ENABLE 1 */
sfr at 0xE7 EIE2; /* EXTENDED INTERRUPT ENABLE 2 */
sfr at 0xE8 ADC0CN; /* ADC0 CONTROL */
sfr at 0xE8 ADC2CN; /* ADC2 CONTROL */
sfr at 0xE8 P6; /* PORT 6 LATCH */
sfr at 0xE9 PCA0CPL2; /* PCA MODULE 2 
CAPTURE/COMPARE LOW BYTE */
sfr at 0xEA PCA0CPH2; /* PCA MODULE 2 
CAPTURE/COMPARE HIGH BYTE */
sfr at 0xEB PCA0CPL3; /* PCA MODULE 3 
CAPTURE/COMPARE LOW BYTE */
sfr at 0xEC PCA0CPH3; /* PCA MODULE 3 
CAPTURE/COMPARE HIGH BYTE */
sfr at 0xED PCA0CPL4; /* PCA MODULE 4 
CAPTURE/COMPARE LOW BYTE */
sfr at 0xEE PCA0CPH4; /* PCA MODULE 4 
CAPTURE/COMPARE HIGH BYTE */
sfr at 0xEF RSTSRC; /* RESET SOURCE */
sfr at 0xF0 B; /* B REGISTER */
sfr at 0xF6 EIP1; /* EXTERNAL INTERRUPT PRIORITY 1 */
sfr at 0xF7 EIP2; /* EXTERNAL INTERRUPT PRIORITY 2 */
sfr at 0xF8 P7; /* PORT 7 LATCH */
sfr at 0xF8 SPI0CN; /* SPI CONTROL */
sfr at 0xF9 PCA0L; /* PCA COUNTER LOW BYTE */
sfr at 0xFA PCA0H; /* PCA COUNTER HIGH BYTE */
sfr at 0xFB PCA0CPL0; /* PCA MODULE 0 
CAPTURE/COMPARE LOW BYTE */
sfr at 0xFC PCA0CPH0; /* PCA MODULE 0 
CAPTURE/COMPARE HIGH BYTE */
sfr at 0xFD PCA0CPL1; /* PCA MODULE 1 
CAPTURE/COMPARE LOW BYTE */
sfr at 0xFE PCA0CPH1; /* PCA MODULE 1 
CAPTURE/COMPARE HIGH BYTE */
sfr at 0xFF WDTCN; /* WATCHDOG TIMER CONTROL */


/* Bit Definitions */

/* TCON 0x88 */
sbit at 0x8F  TF1;  /* TIMER 1 OVERFLOW FLAG */
sbit at 0x8E  TR1;  /* TIMER 1 ON/OFF CONTROL */
sbit at 0x8D  TF0;  /* TIMER 0 OVERFLOW FLAG */
sbit at 0x8C  TR0;  /* TIMER 0 ON/OFF CONTROL */
sbit at 0x8B  IE1;  /* EXT. INTERRUPT 1 EDGE FLAG */
sbit at 0x8A  IT1;  /* EXT. INTERRUPT 1 TYPE */
sbit at 0x89  IE0;  /* EXT. INTERRUPT 0 EDGE FLAG */
sbit at 0x88  IT0;  /* EXT. INTERRUPT 0 TYPE */

/* CPT0CN 0x88 */
sbit at 0x8F  CP0EN;  /* COMPARATOR 0 ENABLE */
sbit at 0x8E  CP0OUT;  /* COMPARATOR 0 OUTPUT */
sbit at 0x8D  CP0RIF;  /* COMPARATOR 0 RISING EDGE 
INTERRUPT */
sbit at 0x8C  CP0FIF;  /* COMPARATOR 0 FALLING EDGE 
INTERRUPT */
sbit at 0x8B  CP0HYP1;  /* COMPARATOR 0 POSITIVE 
HYSTERISIS 1 */
sbit at 0x8A  CP0HYP0;  /* COMPARATOR 0 POSITIVE 
HYSTERISIS 0 */
sbit at 0x89  CP0HYN1;  /* COMPARATOR 0 NEGATIVE 
HYSTERISIS 1 */
sbit at 0x88  CP0HYN0;  /* COMPARATOR 0 NEGATIVE 
HYSTERISIS 0 */

/* CPT1CN 0x88 */
sbit at 0x8F  CP1EN;  /* COMPARATOR 1 ENABLE */
sbit at 0x8E  CP1OUT;  /* COMPARATOR 1 OUTPUT */
sbit at 0x8D  CP1RIF;  /* COMPARATOR 1 RISING EDGE 
INTERRUPT */
sbit at 0x8C  CP1FIF;  /* COMPARATOR 1 FALLING EDGE 
INTERRUPT */
sbit at 0x8B  CP1HYP1;  /* COMPARATOR 1 POSITIVE 
HYSTERISIS 1 */
sbit at 0x8A  CP1HYP0;  /* COMPARATOR 1 POSITIVE 
HYSTERISIS 0 */
sbit at 0x89  CP1HYN1;  /* COMPARATOR 1 NEGATIVE 
HYSTERISIS 1 */
sbit at 0x88  CP1HYN0;  /* COMPARATOR 1 NEGATIVE 
HYSTERISIS 0 */

/* FLSTAT 0x88 */
sbit at 0x88  FLHBUSY;  /* FLASH BUSY */

/* SCON0 0x98 */
sbit at 0x9F  SM00;  /* UART 0 MODE 0 */
sbit at 0x9E  SM10;  /* UART 0 MODE 1 */
sbit at 0x9D  SM20;  /* UART 0 MULTIPROCESSOR EN */
sbit at 0x9C  REN0;  /* UART 0 RX ENABLE */
sbit at 0x9B  TB80;  /* UART 0 TX BIT 8 */
sbit at 0x9A  RB80;  /* UART 0 RX BIT 8 */
sbit at 0x99  TI0;  /* UART 0 TX INTERRUPT FLAG */
sbit at 0x98  RI0;  /* UART 0 RX INTERRUPT FLAG */

/* SCON1 0x98 */
sbit at 0x9F  S1MODE;  /* UART 1 MODE */
sbit at 0x9D  MCE1;  /* UART 1 MCE */
sbit at 0x9C  REN1;  /* UART 1 RX ENABLE */
sbit at 0x9B  TB81;  /* UART 1 TX BIT 8 */
sbit at 0x9A  RB81;  /* UART 1 RX BIT 8 */
sbit at 0x99  TI1;  /* UART 1 TX INTERRUPT FLAG */
sbit at 0x98  RI1;  /* UART 1 RX INTERRUPT FLAG */

/* IE 0xA8 */
sbit at 0xAF  EA;  /* GLOBAL INTERRUPT ENABLE */
sbit at 0xAD  ET2;  /* TIMER 2 INTERRUPT ENABLE */
sbit at 0xAC  ES0;  /* UART0 INTERRUPT ENABLE */
sbit at 0xAB  ET1;  /* TIMER 1 INTERRUPT ENABLE */
sbit at 0xAA  EX1;  /* EXTERNAL INTERRUPT 1 ENABLE */
sbit at 0xA9  ET0;  /* TIMER 0 INTERRUPT ENABLE */
sbit at 0xA8  EX0;  /* EXTERNAL INTERRUPT 0 ENABLE */

/* IP 0xB8 */
sbit at 0xBD  PT2;  /* TIMER 2 PRIORITY */
sbit at 0xBC  PS;  /* SERIAL PORT PRIORITY */
sbit at 0xBB  PT1;  /* TIMER 1 PRIORITY */
sbit at 0xBA  PX1;  /* EXTERNAL INTERRUPT 1 PRIORITY 
*/
sbit at 0xB9  PT0;  /* TIMER 0 PRIORITY */
sbit at 0xB8  PX0;  /* EXTERNAL INTERRUPT 0 PRIORITY 
*/

/* SMB0CN 0xC0 */
sbit at 0xC7  BUSY;  /* SMBUS 0 BUSY */
sbit at 0xC6  ENSMB;  /* SMBUS 0 ENABLE */
sbit at 0xC5  STA;  /* SMBUS 0 START FLAG */
sbit at 0xC4  STO;  /* SMBUS 0 STOP FLAG */
sbit at 0xC3  SI;  /* SMBUS 0 INTERRUPT PENDING FLAG 
*/
sbit at 0xC2  AA;  /* SMBUS 0 ASSERT/ACKNOWLEDGE 
FLAG */
sbit at 0xC1  SMBFTE;  /* SMBUS 0 FREE TIMER ENABLE 
*/
sbit at 0xC0  SMBTOE;  /* SMBUS 0 TIMEOUT ENABLE */

/* MAC0STA 0xC0 */
sbit at 0xC3  MAC0HO;  /* MAC0 HARD OVERFLOW */
sbit at 0xC2  MAC0Z;  /* MAC0 ZERO */
sbit at 0xC1  MAC0SO;  /* MAC0 SOFT OVERFLOW */
sbit at 0xC0  MAC0N;  /* MAC0 NEGATIVE */

/* TMR2CN 0xC8 */
sbit at 0xCF  TF2;  /* TIMER 2 OVERFLOW FLAG */
sbit at 0xCE  EXF2;  /* TIMER 2 EXTERNAL FLAG */
sbit at 0xCB  EXEN2;  /* TIMER 2 EXTERNAL ENABLE 
FLAG */
sbit at 0xCA  TR2;  /* TIMER 2 ON/OFF CONTROL */
sbit at 0xC9  CT2;  /* TIMER 2 COUNTER SELECT */
sbit at 0xC8  CPRL2;  /* TIMER 2 CAPTURE SELECT */

/* TMR3CN 0xC8 */
sbit at 0xCF  TF3;  /* TIMER 3 OVERFLOW FLAG */
sbit at 0xCE  EXF3;  /* TIMER 3 EXTERNAL FLAG */
sbit at 0xCB  EXEN3;  /* TIMER 3 EXTERNAL ENABLE 
FLAG */
sbit at 0xCA  TR3;  /* TIMER 3 ON/OFF CONTROL */
sbit at 0xC9  CT3;  /* TIMER 3 COUNTER SELECT */
sbit at 0xC8  CPRL3;  /* TIMER 3 CAPTURE SELECT */

/* TMR4CN 0xC8 */
sbit at 0xCF  TF4;  /* TIMER 4 OVERFLOW FLAG */
sbit at 0xCE  EXF4;  /* TIMER 4 EXTERNAL FLAG */
sbit at 0xCB  EXEN4;  /* TIMER 4 EXTERNAL ENABLE 
FLAG */
sbit at 0xCA  TR4;  /* TIMER 4 ON/OFF CONTROL */
sbit at 0xC9  CT4;  /* TIMER 4 COUNTER SELECT */
sbit at 0xC8  CPRL4;  /* TIMER 4 CAPTURE SELECT */

/* PSW 0xD0 */
sbit at 0xD7  CY;  /* CARRY FLAG */
sbit at 0xD6  AC;  /* AUXILIARY CARRY FLAG */
sbit at 0xD5  F0;  /* USER FLAG 0 */
sbit at 0xD4  RS1;  /* REGISTER BANK SELECT 1 */
sbit at 0xD3  RS0;  /* REGISTER BANK SELECT 0 */
sbit at 0xD2  OV;  /* OVERFLOW FLAG */
sbit at 0xD1  F1;  /* USER FLAG 1 */
sbit at 0xD0  P;  /* ACCUMULATOR PARITY FLAG */

/* PCA0CN 0xD8 */
sbit at 0xDF  CF;  /* PCA 0 COUNTER OVERFLOW FLAG */
sbit at 0xDE  CR;  /* PCA 0 COUNTER RUN CONTROL BIT 
*/
sbit at 0xDD  CCF5;  /* PCA 0 MODULE 5 INTERRUPT 
FLAG */
sbit at 0xDC  CCF4;  /* PCA 0 MODULE 4 INTERRUPT 
FLAG */
sbit at 0xDB  CCF3;  /* PCA 0 MODULE 3 INTERRUPT 
FLAG */
sbit at 0xDA  CCF2;  /* PCA 0 MODULE 2 INTERRUPT 
FLAG */
sbit at 0xD9  CCF1;  /* PCA 0 MODULE 1 INTERRUPT 
FLAG */
sbit at 0xD8  CCF0;  /* PCA 0 MODULE 0 INTERRUPT 
FLAG */

/* ADC0CN 0xE8 */
sbit at 0xEF  AD0EN;  /* ADC 0 ENABLE */
sbit at 0xEE  AD0TM;  /* ADC 0 TRACK MODE */
sbit at 0xED  AD0INT;  /* ADC 0 EOC INTERRUPT FLAG */
sbit at 0xEC  AD0BUSY;  /* ADC 0 BUSY FLAG */
sbit at 0xEB  AD0CM1;  /* ADC 0 CONVERT START MODE 
BIT 1 */
sbit at 0xEA  AD0CM0;  /* ADC 0 CONVERT START MODE 
BIT 0 */
sbit at 0xE9  AD0WINT;  /* ADC 0 WINDOW INTERRUPT 
FLAG */
sbit at 0xE8  AD0LJST;  /* ADC 0 RIGHT JUSTIFY DATA 
BIT */

/* ADC2CN 0xE8 */
sbit at 0xEF  AD2EN;  /* ADC 2 ENABLE */
sbit at 0xEE  AD2TM;  /* ADC 2 TRACK MODE */
sbit at 0xED  AD2INT;  /* ADC 2 EOC INTERRUPT FLAG */
sbit at 0xEC  AD2BUSY;  /* ADC 2 BUSY FLAG */
sbit at 0xEB  AD2CM2;  /* ADC 2 CONVERT START MODE 
BIT 2 */
sbit at 0xEA  AD2CM1;  /* ADC 2 CONVERT START MODE 
BIT 1 */
sbit at 0xE9  AD2CM0;  /* ADC 2 CONVERT START MODE 
BIT 0 */
sbit at 0xE8  AD2WINT;  /* ADC 2 WINDOW INTERRUPT 
FLAG */

/* SPI0CN 0xF8 */
sbit at 0xFF  SPIF;  /* SPI 0 INTERRUPT FLAG */
sbit at 0xFE  WCOL;  /* SPI 0 WRITE COLLISION FLAG */
sbit at 0xFD  MODF;  /* SPI 0 MODE FAULT FLAG */
sbit at 0xFC  RXOVRN;  /* SPI 0 RX OVERRUN FLAG */
sbit at 0xFB  NSSMD1;  /* SPI 0 SLAVE SELECT MODE 1 
*/
sbit at 0xFA  NSSMD0;  /* SPI 0 SLAVE SELECT MODE 0 
*/
sbit at 0xF9  TXBMT;  /* SPI 0 TX BUFFER EMPTY FLAG 
*/
sbit at 0xF8  SPIEN;  /* SPI 0 SPI ENABLE */


/* SFR PAGE DEFINITIONS */

#define CONFIG_PAGE       0x0F    /* SYSTEM AND PORT 
CONFIGURATION PAGE */
#define LEGACY_PAGE       0x00    /* LEGACY SFR PAGE 
*/
#define TIMER01_PAGE      0x00    /* TIMER 0 AND 
TIMER 1 */
#define CPT0_PAGE         0x01    /* COMPARATOR 0 */
#define CPT1_PAGE         0x02    /* COMPARATOR 1 */
#define UART0_PAGE        0x00    /* UART 0 */
#define UART1_PAGE        0x01    /* UART 1 */
#define SPI0_PAGE         0x00    /* SPI 0 */
#define EMI0_PAGE         0x00    /* EXTERNAL MEMORY 
INTERFACE */
#define ADC0_PAGE         0x00    /* ADC 0 */
#define ADC2_PAGE         0x02    /* ADC 2 */
#define SMB0_PAGE         0x00    /* SMBUS 0 */
#define TMR2_PAGE         0x00    /* TIMER 2 */
#define TMR3_PAGE         0x01    /* TIMER 3 */
#define TMR4_PAGE         0x02    /* TIMER 4 */
#define DAC0_PAGE         0x00    /* DAC 0 */
#define DAC1_PAGE         0x01    /* DAC 1 */
#define PCA0_PAGE         0x00    /* PCA 0 */
#define PLL0_PAGE         0x0F    /* PLL 0 */
#define MAC0_PAGE         0x03    /* MAC 0 */

/* P0 0x80 */
sbit at 0x80 P0_0;
sbit at 0x81 P0_1;
sbit at 0x82 P0_2;
sbit at 0x83 P0_3;
sbit at 0x84 P0_4;
sbit at 0x85 P0_5;
sbit at 0x86 P0_6;
sbit at 0x87 P0_7;

/* P1 0x90 */
sbit at 0x90 P1_0;
sbit at 0x91 P1_1;
sbit at 0x92 P1_2;
sbit at 0x93 P1_3;
sbit at 0x94 P1_4;
sbit at 0x95 P1_5;
sbit at 0x96 P1_6;
sbit at 0x97 P1_7;

/* P2 0xA0 */
sbit at 0xA0 P2_0;
sbit at 0xA1 P2_1;
sbit at 0xA2 P2_2;
sbit at 0xA3 P2_3;
sbit at 0xA4 P2_4;
sbit at 0xA5 P2_5;
sbit at 0xA6 P2_6;
sbit at 0xA7 P2_7;

/* P3 0xB0 */
sbit at 0xB0 P3_0;
sbit at 0xB1 P3_1;
sbit at 0xB2 P3_2;
sbit at 0xB3 P3_3;
sbit at 0xB4 P3_4;
sbit at 0xB5 P3_5;
sbit at 0xB6 P3_6;
sbit at 0xB7 P3_7;

/* P4 0xC8 */
sbit at 0xC8 P4_0;
sbit at 0xC9 P4_1;
sbit at 0xCA P4_2;
sbit at 0xCB P4_3;
sbit at 0xCC P4_4;
sbit at 0xCD P4_5;
sbit at 0xCE P4_6;
sbit at 0xCF P4_7;

/* P5 0xD8 */
sbit at 0xD8 P5_0;
sbit at 0xD9 P5_1;
sbit at 0xDA P5_2;
sbit at 0xDB P5_3;
sbit at 0xDC P5_4;
sbit at 0xDD P5_5;
sbit at 0xDE P5_6;
sbit at 0xDF P5_7;

/* P6 0xE8 */
sbit at 0xE8 P6_0;
sbit at 0xE9 P6_1;
sbit at 0xEA P6_2;
sbit at 0xEB P6_3;
sbit at 0xEC P6_4;
sbit at 0xED P6_5;
sbit at 0xEE P6_6;
sbit at 0xEF P6_7;

/* P7 0xF8 */
sbit at 0xF8 P7_0;
sbit at 0xF9 P7_1;
sbit at 0xFA P7_2;
sbit at 0xFB P7_3;
sbit at 0xFC P7_4;
sbit at 0xFD P7_5;
sbit at 0xFE P7_6;
sbit at 0xFF P7_7;

volatile unsigned data at 0x82 DP      ;// = 
0x82;                 // data pointer
volatile unsigned data at 0xBE ADC0    ;// = 
0xbe;                 // ADC0 data
volatile unsigned data at 0xC4 ADC0GT  ;// = 
0xc4;                 // ADC0 greater than window
volatile unsigned data at 0xC6 ADC0LT  ;// = 
0xc6;                 // ADC0 less than window
volatile unsigned data at 0xCA RCAP2   ;// = 
0xca;                 // Timer2 capture/reload
volatile unsigned data at 0xCA RCAP3   ;// = 
0xca;                 // Timer3 capture/reload
volatile unsigned data at 0xCA RCAP4   ;// = 
0xca;                 // Timer4 capture/reload
volatile unsigned data at 0xCC TMR2    ;// = 
0xcc;                 // Timer2
volatile unsigned data at 0xCC TMR3    ;// = 
0xcc;                 // Timer3
volatile unsigned data at 0xCC TMR4    ;// = 
0xcc;                 // Timer4
volatile unsigned data at 0xD2 DAC0    ;// = 
0xd2;                 // DAC0 data
volatile unsigned data at 0xD2 DAC1    ;// = 
0xd2;                 // DAC1 data
volatile unsigned data at 0xE1 PCA0CP5 ;// = 
0xe1;                 // PCA0 Module 5 capture
volatile unsigned data at 0xE9 PCA0CP2 ;// = 
0xe9;                 // PCA0 Module 2 capture
volatile unsigned data at 0xEB PCA0CP3 ;// = 
0xeb;                 // PCA0 Module 3 capture
volatile unsigned data at 0xED PCA0CP4 ;// = 
0xed;                 // PCA0 Module 4 capture
volatile unsigned data at 0xF9 PCA0    ;// = 
0xf9;                 // PCA0 counter
volatile unsigned data at 0xFB PCA0CP0 ;// = 
0xfb;                 // PCA0 Module 0 capture
volatile unsigned data at 0xFD PCA0CP1 ;// = 
0xfd;                 // PCA0 Module 1 capture


-- ... --
my own version of atol just to see if it was the included 
function:
long atol(char *str)
{
  int i;
  long value;
  int len;
  long pos;
  pos=1;
  value=0;
  len=strlen(str);
  for (i=len;i>0;i--)
  {
    value+=(str[i-1]-'0')*pos;
    pos*=(long)10;
  }
  return value;
}


----------------------------------------------------------------------

>Comment By: James Davis (davija)
Date: 2004-11-01 08:28

Message:
Logged In: YES 
user_id=282346

Thanks for the workaround info.  It works so far (as far as I 
can tell).  I knew it wasn't with atoi/atol because of my 
functions doing the same thing.  I just didn't know where to 
look.

Thanks again.

----------------------------------------------------------------------

Comment By: Frieder Ferlemann (frief)
Date: 2004-11-01 08:08

Message:
Logged In: YES 
user_id=589052

Hi,
this seems to be caused by a bug in the (s)printf routine,
the attached file (when copied into
sdcc/support/regression/tests/) reproduces your problem
within the regression tests.
As a workaround you could try using printf_fast for now. 
(Let the preprocessor do it: #define printf printf_fast).


----------------------------------------------------------------------

You can respond by visiting: 
https://sourceforge.net/tracker/?func=detail&atid=100599&aid=1057979&group_id=599