From: Vitaly M. <v.m...@gm...> - 2008-12-04 14:22:59
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At Wed, 3 Dec 2008 16:31:39 -0500, Paul Khuong wrote: Got further question, now regarding to values passing between VOPs (?) > (defun test (x) > (declare (type (simple-array (unsigned-byte 8) 1) x) > (optimize speed (safety 0))) > (let ((length (sb-c::widenify (length x))) > (ix (sb-c::widenify 0)) > (sum (sb-c::widenify 0))) > (declare (type (unsigned-byte 64) length ix sum)) > (loop while (< ix length) > do (incf sum (aref x ix)) > (incf ix (sb-c::widenify 1)) > finally (return sum)))) > > ; 045174DF: 488B4AF9 MOV RCX, [RDX-7] ; no-arg- > parsing entry point > ; 4E3: 48C1F903 SAR RCX, 3 > ; 4E7: 488BD9 MOV RBX, RCX > ; 4EA: 31C0 XOR EAX, EAX > ; 4EC: 31C9 XOR ECX, ECX > ; 4EE: EB14 JMP L1 ==========> > ; 4F0: L0: 488BF0 MOV RSI, RAX > ; 4F3: 480FB6743201 MOVZX RSI, BYTE PTR [RDX+RSI+1] <========== > ; 4F9: 4801F1 ADD RCX, RSI > ; 4FC: BE01000000 MOV ESI, 1 > ; 501: 4801F0 ADD RAX, RSI > ; 504: L1: 4839D8 CMP RAX, RBX > ; 507: 72E7 JB L0 Selected fragment in IR2 representation is: 0: WORD-MOVE IX!30[RCX] => t34[RAX] 1: WORD-MOVE t34[RAX] => t35[RAX] 2: DATA-VECTOR-REF/SIMPLE-ARRAY-UNSIGNED-BYTE-8 X!11[RSI] t35[RAX] {0} => t36[RAX] The second `move' was eliminated by conditional load (:load-if (not (location= ...))), but why do we need to pass already loaded value in another register? Is it some kind of transformation? I can only imagine, it is done so, because proper register can be changed in VOP by side effect (that's not true for data-vector-ref). -- wbr, Vitaly |