A few XDL questions, and using RapidSmith

2014-04-24
2014-05-06
  • Vincent Mirian
    Vincent Mirian
    2014-04-24

    Hi all,

    First of all, thanks for a great tool. RapidSmith is well documented and works nicely right out-of-the-box.

    Second, I would like to use RapidSmith to profile the resource utilization of a few components in my design. For example, I would like to retrieve the amount of switch blocks and wires for a given component. Since Xilinx does a descent job of preserving the name of the component in the net, I can use the net name (or inpin and outpin of a net) to associate the net to the component. Then, for each net I would like to get the switch block and wire used (as well as the length of the wire). However, I am uncertain how these primitives (switch block and wires) are represented in RapidSmith. Are the switch blocks modelled using Tiles? Also, in regards to the wires how is the mapping done from PIP to WireConnection?

    Finally, great work guys, and keep it up! :)

    Thanks again.

     
  • Chris Lavin
    Chris Lavin
    2014-04-25

    Hi Vincent,

    Thank you for the compliments, its nice to know that the work is appreciated!

    To answer your inquiry, I believe what you refer to as a 'switch block' is represented mostly as a tile in RapidSmith. In many of the Xilinx families, a tile has a type, the most popular 'switch block' type is called "INT". INT or interconnect tiles typically will accompany (in a paired column) any CLB, DSP, BRAM column of tiles. Often what you'll see in the XDL are a list of PIPs that have a tile name, such as "INT_X4Y5" and then the name of two wires that are being connected by the PIP in that particular tile.

    Sometimes you might see PIPs that exist in other tile types (like CLB or DSP), however, they may not actually affect the bitstream. Sometimes these are called fake PIPs because they simply provide connectivity information.

    The WireConnection object is more of an internal class within RapidSmith to help provide connectivity information. It simply describes how wires connect, often to outside of a tile. PIPs are purely intra-tile connectivity. WireConnections are either intra- or inter-tile connectivity. A PIP always has a corresponding WireConnection, but WireConnections may not always have a corresponding PIP (in the inter-tile case).

    I'm not sure exactly how you want to characterize the usage of the components in your design, but if you are counting usage, you may also want to count instances within your design. If you share a little more detail about what you are interested in counting, I might be able to share some tips on how to approach it.

    One last warning, the names given in XDL are semi-accurate, but not always definitive in determining what part of your design they were derived from. Probably good enough to get some decent estimates, but keep in mind that there will be some margin of error counting things this way.

    Chris

     
  • Vincent Mirian
    Vincent Mirian
    2014-04-25

    Hi Chris,

    Thank you for the quick reply.

    Essentially, my goal is to retrieve the number of switch blocks and wires (and their length) for a set of nets (an approximation at the moment should be sufficient for the moment). So far to calculate the number of switch blocks, I do the following (high level pseudo-code):

    For each net N do
    For each pip P in N do
    if P.getTile.getType == INT then
    add P.getTile in list tileList
    end if
    end for
    end for
    remove duplicate in tileList
    tileList.size returns the number of switch blocks used by the set of nets.

    Now I would like to retrieve the number of wires (a.k.a. global routing wires and inter-tile connections) used in the same set of nets. I also would like to retrieve the length of the wires, not the length of its connection, but its maximum length. However, I am having difficulty completing this task. The following is the pseudo-code for this task (it is similar to that above):

    For each net N do
    For each pip P in N do
    if P.getTile.getType == INT then
    wire = P.getStartWire
    if wire is an inter-tile connection then
    add <wire, wire.getLength=""> to wireList
    end if
    end if
    end for
    end for

    In regards tothe above pseudo-code, I have difficulty deciphering when a wire is an inter-tile connection, and the connection length potential of the wire.

    I'm looking into the WireConnections class, but I am not able to figure out how to use it to complete the above pseudo-code.

    Any help would be appreciated. Thanks :)

     
  • Chris Lavin
    Chris Lavin
    2014-05-03

    Hi Vincent,

    I found some spare time to try and implement some of what you were trying to tabulate about a design's routing. I have attached an example RapidSmith program in CountingExample.java which worked for a Virtex 4 design I had laying around.

    The one caveat is that it does not support long lines, I left that up to you. Long lines can be driven by multple points along the resource so some extra book keeping is required to make sure you don't count the same wire twice.

    This code is also dependent on the WireType accuracy which may or may not work the best for older or newer architectures. Mostly I can say they are correct for Virtex 4 and 5.

    Enjoy.

    Chris

     
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  • Vincent Mirian
    Vincent Mirian
    2014-05-06

    Hi Chris,

    Thank you for the response. Although I am targeting Virtex 6 devices, your code is useful.

    To recap, my goal is to calculate the number of global routing wires a net uses, and the the length of these wires. In a Virtex 6 device, the global routing wires length are 1, 2, 4 CLB in length. To do so, I am traversing a net using Breath First Search (BFS). For each pip of a net, if the connection is a route-through or a intra-tile (local connection to the CLB) I ignore the wirelength, since it is not a global routing wire. To calculate the wirelength, I count the number of switchbox 'hops' between the connections. Since the device plan is irregular, I use a row and column in the device that has is uniform with the switchbox and logic block (i.e. row 6 and column 6 of Virtex 6 LX240T1156).

    When experimenting this approach with nets, I do see wires of length greater than 4 'CLB lengths', such 5-9 and 16. The larger 'CLB lengths' occur since some wires are diagonal and span a few CLBs in the vertical and horizontal.

    Can anyone provide feedback on this approach?

    Thank you. It is much appreciated.