#4 Fixes for the simulation of VHDL files in a schematic

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nobody
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2012-12-15
2009-10-03
Jonas
No

Hi

I made 2 fixes for the simulations with VHDL files on the schematic.
- I added the support for the vectors
- Now the input signals will be displayed at left and the output signals at right of the component, according to the convention.

I think that this time the concept is good, and the fixes were made in a good manner.
How do you think ?

Bye
Jonas

Discussion

  • Jonas
    Jonas
    2009-10-03

    And I forgot to say that this patch is to be applied to the latest CVS

     
  • Jonas
    Jonas
    2009-10-03

    The 2nd version of the patch fix something that can leed to segmentation fault.

     
  • Hi

    I have one more fix :
    The name of a new component made by copy and paste has at first the name of the component it was copied from, then later it gets its final name
    My patch need to know the component name, but the previous versions read it too early in case of a copy and paste.
    This 3rd version of my patch read the component name at simulation time to fix this problem.

     
  • Jonas
    Jonas
    2009-10-04

    Fixes for VHDL simulation

     
    Attachments
  •  gatisg
    gatisg
    2009-10-11

    TY jonas813!
    Can You plz place here updated binarie[s]?

     
  • Jonas
    Jonas
    2009-10-12

    Hi

    You can uncompress the compressed folder in http://www.datafilehost.com/download-71e72d8d.html in /opt.
    I use debian testing on i386. If you have a different distro, it may not work.

     
  •  gatisg
    gatisg
    2009-10-14

    Hi Jonas!

    1. Thank You for an immediate answer, but actually I'm Win based :/
    Some time ago I tried to compile (on Win and then on Cygwin) qucs by myself, but got nightmare with QT libraries, so now I better use pros compiled versions.
    So if any can do it, plz place somewhere recompiled win binaries.
    2. If qucs still does not support buses, then that should be interesting to see, how vectors are implemented - I suppose as a single wire connections...
    3. Placing inputs at left un outputs at right by default is nice feature - rearranging ports is not nicest part of component design :)

    Regards ~
    Gatis

     
  • Hi

    I saw there was some changes for the vhdl in the CVS, so I just downloaded the last CVS, but it is still not possible to simulate a schematic that has a vhdl file inserted with logic vectors in the entity .

    Bye
    Jonas

     
  • Stefan Jahn
    Stefan Jahn
    2009-11-01

    Can you please provide such an entity?

     
  • Jonas
    Jonas
    2009-11-01

    Hi

    Here is a vhdl file with such an entity :

    Library IEEE;

    USE ieee.std_logic_1164.all;

    Entity Serpent is Port(

    clk : IN std\_logic;
    aff : OUT std\_logic\_vector\(6 downto 0\)\);
    

    End Entity Serpent;

    Architecture arch_Serpent of Serpent is

    Signal D : std\_logic\_vector\(2 downto 0\):="000";
    Signal Q : std\_logic\_vector\(2 downto 0\):="000";
    

    Begin

    ------- COPIE DE D DANS Q A CHAQUE FLANC MONTANT D'HORLOGE
    FF_Q : process(clk) is

    begin
    
        if rising\_edge\(clk\) then
    
            Q <= D;
        end if;
    
    End process FF\_Q;
    

    ------- CALCULS DES ENTREES ET DE L'AFFICHAGE
    FF_D_Aff : process(Q) is

    begin
    
        case Q is
    
        when "000" =>
            aff <= "0000100";
            D <= "001";
    
        when "001" =>
            aff <= "0000010";
            D <= "010";
    
        when "010" =>
            aff <= "1000000";
            D <= "011";
    
        when "011" =>
            aff <= "0100000";
            D <= "100";
    
        when "100" =>
            aff <= "0010000";
            D <= "101";
    
        when "101" =>
            aff <= "0001000";
            D <= "110";
    
        when "110" =>
            aff <= "0000100";
            D <= "111";
    
        when "111" =>
            aff <= "0000001";
            D <= "000";
    
        when others => D <= "000";
    
        end case;
    
    End Process FF\_D\_Aff;
    

    End Architecture arch_Serpent;

    Bye
    Jonas