Hello,
for implementing a "user defined model" it would be very useful to use Verilog-A as a description language.
Otherwise it will be very difficult to implement all models in C++, esp. the user of qucs who are not familiar with C++.
For my opinion Verlog-A is very simple and straight forward.
Maybe you will find futher infomation at: http://www.v-ms.com/v2000.html (GNU Verilog-A) or at google

They have done already a lot of work. I don't know if you can reused the code?

jens


Stefan Jahn schrieb:
Hello Pierre!

  
Thank for the advise, I get the pakages from ATG as Jens Fluke suggest
me to do and it works now.
    

Oh, erm.  I oversaw this possiblity...  But my suggestion will be good
for setting up a development environment.

  
I am really impressed by this software, I am a `everyday user` of
Eagleware and ADS circuit simulator and there is not much more work to
reach them !
    

Not by far I suppose?

  
By the way I was thinking of contributing the the developpement of
qucs. I was thinking for example at yeild definition and optimisation
or more specificaly to `user models` (the ability for a user to write
his own model and link a n-port box to this model ).
    

I think these are good ideas, but right now qucs is not yet ready for
this... Proove me wrong and make your suggestions.  Have you experiences
in this field?

Cheers, Stefan.




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