I wanted to simulate a simple reset circuit build from 3 bit asynchronous timer. When MSB of the counter goes high reset should go high and the counter should start counting from 000. But in my case no reset is comming. Could somebody check my circuit. it is in attachment
I am not really sure what you are trying to achieve.
Aren't your D flip-flops expecting a synchronous reset? In other works it should reset provided it sees your (asynchronous) clock signal.
The counter counts from 0 to 7.. what i want was actually to reset the counter in transition from 4 to 5, thats why I fed back inverted msb of the counter to the R pins of DFFs. I think I solved the problem by inserting us delay to the NOT gate