How to make a vhdl simulation

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Jonas
2009-06-26
2012-12-15
  • Jonas
    Jonas
    2009-06-26

    Hello

    I am using the 0.0.15 version of Qucs.
    When I insert a vhdl file on a schematic, I need to set some generic variable in this block and I don't know what to put to make it work.

    Thanks in advance for your help
    Jonas

     
  • Jonas
    Jonas
    2009-09-19

    Hello

    Here is the schematic I would like to simulate :

    And the vhdl file inserted into the schematic :

    And the netlist I have when I want to simulate :

    In the netlist the following line makes the simulation fail :

    X1: entity add_2bits generic map (, , , ) port map (net_net0, net_net1, netsortie1, netsortie2);

    I am a beginner in vhdl, but it seems to me that if I didn't have any generics used in my vhdl code, then there shouldn't be the instruction "generic map" in this line.

    Bye
    Jonas

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  • I had the same problem: see my two entries (tangofoxtrot) on the Open Discussion thread.
    Basically, its a bug in qucs that causes it to think there are generics when there aren't. To fix it,one needs to install the fixes in cvs 2009-04-29 vhdlfile.cpp.
    I am running win32 Qucs 0.0.15 that I downloaded as a self installing .exe and don't know how to do this

     
  • Jonas
    Jonas
    2009-09-28

    Hello
    Thanks for your answer

    I am going to compile the svn version.

    Bye
    Jonas

     
  • Vitaly Hryb
    Vitaly Hryb
    2012-03-23

    I know only one workaround.
    Generic map in VHDL is a template for C++. I don't know why Qucs adding generic map( … ) but to compile and get simulation just add generic( param: type ) to your entity. Then specify any parameter value for your VHDL param A.

    Example of workaround:


    entity Entity is
    generic( A : bit ); - <-- generic param
    port ( d : out std_logic );
    end entity ServoTester;

    … generic map ( '0' ) … <- any param value, used '0'