qucs vhdl problem

2009-09-11
2012-12-15
  • I am trying to create a digital subcircuit based on a vhdl file. The actual component is a 4bit pattern generator that is an example I downloaded. I have successfully created a schematic and symbol for the pattern generator and included it in another schematic that I am using as a testfixture.

    When I try to simulate the result, QUCS generates a netlist containing an entry that the parser chokes on. The offending entry is:
      X1: entity patgen_4bit generic map (, , , , , ) port map (net_net0, net_net1, net_net2, net_net3, net_net4, net_net5);
    It does not like the map (,,,,,) part.

    As you can see below, I'm not explicitly using generics.

    I have included the entire netlist list below. I'm not sure what the Sub_PatGen4Bit entity is all about.

    -- Qucs 0.0.15  C:/Documents and Settings/Server/.qucs/DigitalExps_prj/TestPatGen4Bit.sch

    -- 4 bit pattern generator (see example3)
    entity patgen_4bit is
    port ( RESET, CLOCK : in bit ;
    B0 , B1 , B2 , B3 : out bit
    ) ;
    end entity patgen_4bit ;
    --
    architecture behavioural of patgen_4bit is
    begin
    p1 : process (RESET, CLOCK) is
    variable present_state , next_state :
        bit_vector (3 downto 0):= "0000" ;
    begin
    if (RESET ='1' ) then next_state := "0000" ;
    elsif (CLOCK' event and CLOCK='1') then
    present_state := next_state ;
    case present_state is
    when "0000" => next_state := "0001" ;
    when "0001" => next_state := "0010" ;
    when "0010" => next_state := "0011" ;
    when "0011" => next_state := "0100" ;
    when "0100" => next_state := "0101" ;
    when "0101" => next_state := "0110" ;
    when "0110" => next_state := "0111" ;
    when "0111" => next_state := "1000" ;
    when "1000" => next_state := "1001" ;
    when "1001" => next_state := "1010" ;
    when "1010" => next_state := "1011" ;
    when "1011" => next_state := "1100" ;
    when "1100" => next_state := "1101" ;
    when "1101" => next_state := "1110" ;
    when "1110" => next_state := "1111" ;
    when "1111" => next_state := "0000" ;
    end case ;
    end if ;
    B3 <= next_state ( 3 ) ; B2 <= next_state ( 2 ) ;
    B1 <= next_state ( 1 ) ; B0 <= next_state ( 0 ) ;
    end process p1 ;
    end architecture behavioural ;

    library ieee;
    use ieee.std_logic_1164.all;
    entity Sub_PatGen4Bit is
      port (net_net0 : in bit;
            net_net1 : in bit;
            net_outnet_net2 : out bit;
            net_outnet_net3 : out bit;
            net_outnet_net4 : out bit;
            net_outnet_net5 : out bit);
    end entity;
    use work.all;
    architecture Arch_Sub_PatGen4Bit of Sub_PatGen4Bit is
      signal net_net2 : bit;
      signal net_net3 : bit;
      signal net_net4 : bit;
      signal net_net5 : bit;
    begin
      X1: entity patgen_4bit generic map (, , , , , ) port map (net_net0, net_net1, net_net2, net_net3, net_net4, net_net5);
      net_outnet_net2 <= net_net2 or '0';
      net_outnet_net4 <= net_net4 or '0';
      net_outnet_net3 <= net_net3 or '0';
      net_outnet_net5 <= net_net5 or '0';
    end architecture;

    library ieee;
    use ieee.std_logic_1164.all;
    entity TestBench is
    end entity;
    use work.all;

    architecture Arch_TestBench of TestBench is
      signal net_net0 : bit;
      signal net_net1 : bit;
      signal net_net2 : bit;
      signal net_net3 : bit;
      signal net_net4 : bit;
      signal net_net5 : bit;
    begin
      SUB1: entity Sub_PatGen4Bit port map (net_net0, net_net1, net_net2, net_net3, net_net4, net_net5);

      S2:process
      begin
        net_net1 <= '0'; wait for 1 ns;
        net_net1 <= '1'; wait for 1 ns;
      end process;

      S1:process
      begin
        net_net0 <= '1'; wait for 1 ns;
        net_net0 <= '0'; wait for 49 ns;
      end process;
    end architecture;

     
    • Stefan Jahn
      Stefan Jahn
      2009-09-11

      I see the problem.  Somehow Qucs seems to misinterprete 4 additional generics.  IIRC I've seen that problem once already and fixed it in CVS.  But let me investigate that once more.  Thanks for reporting this bug!  I'll let you know the results...

       
    • Stefan Jahn
      Stefan Jahn
      2009-09-11

      Hi again!  Problem was fixed in CVS at 2009-04-29 in "vhdlfile.cpp".

       
  • Thanks for looking into the problem.
    I'm running a win32 qucs, so I'm not sure how to incoporate this fix. Any suggestions how to do this?

     
  • Vitaly Hryb
    Vitaly Hryb
    2012-03-23

    For 0.0.15 I know only one workaround.
    Generic map in VHDL is a template for C++. I don't know why Qucs adding generic map( … ) but to compile and get simulation just add generic( param: type ) to your entity. Then specify any parameter value for your VHDL param.

    Example of workaround:


    entity Entity is
    generic( A : bit ); - <-- generic param
    port ( d : out std_logic );
    end entity ServoTester;

    … generic map ( '0' ) … <- any param value, used '0'