#13 Win32 Infinite loop when exporting VHDL

closed-fixed
None
5
2012-06-20
2011-02-09
Anonymous
No

When i try to generate the vhdl on this project on the windows build, the program freezes, but if you look at the vhdl generated it look likes a infinite loop. The options marked in the export options are:
-Use symbolic names for states
-Use input/output names
-Export state codes
-Synchronous reset
-Negated reset
-use std_logic_1164 package
-Write I/O description into header
-CASE-WHEN notation

The program was tested in a Windows 7 64 bits machine.The program was qsm-0.52 version.

Discussion

  • Project file and vhdl generated

     
    Attachments

  • Anonymous
    2011-03-01

    I have the same problem using Windows 7 32-bit in version 0.52 of the software.

     
  • Stefan Duffner
    Stefan Duffner
    2011-03-02

    • assigned_to: nobody --> sttodu
    • status: open --> open-accepted
     
  • Hello, same problem with XP, I take the example : bin_example.fsm
    And the VHDL generate go to infini with one state copied until crash.

    Output generated (troncated at the end)
    ------------------------------------------------------------------------------------
    -- This file was generated by
    -- Qfsm Version 0.52
    -- (C) Stefan Duffner, Rainer Strobel

    -- Inputs: i_1 i_0
    -- Mealy Outputs: o_1 o_0
    -- State/Output s_out3 s_out2 s_out1 s_out0
    -- State_0 0 0 0 0
    -- State_1 0 0 0 1
    -- State_2 0 0 1 0
    -- State_3 1 0 1 1

    LIBRARY IEEE;

    USE IEEE.std_logic_1164.ALL;

    ENTITY Binary_Machine IS
    PORT (clk: IN std_ulogic;
    rst_n: IN std_ulogic;
    i_1: IN std_ulogic;
    i_0: IN std_ulogic;
    s_out3: OUT std_ulogic;
    s_out2: OUT std_ulogic;
    s_out1: OUT std_ulogic;
    s_out0: OUT std_ulogic;
    o_1: OUT std_ulogic;
    o_0: OUT std_ulogic);
    END Binary_Machine;

    ARCHITECTURE behave OF Binary_Machine IS

    TYPE state_type IS (State_0, State_1, State_2, State_3);
    SIGNAL next_state, current_state : state_type;

    BEGIN
    state_register: PROCESS (rst_n, clk)
    BEGIN
    IF rst_n='0' THEN
    current_state <= State_0;
    ELSIF rising_edge(clk) THEN
    current_state <= next_state;
    END IF;
    END PROCESS;

    next_state_and_output_logic: PROCESS (current_state, i_1, i_0)
    VARIABLE temp_input : std_ulogic_vector(1 DOWNTO 0);
    VARIABLE temp_output : std_ulogic_vector(3 DOWNTO 0);
    VARIABLE temp_mealy_output : std_ulogic_vector(1 DOWNTO 0);
    BEGIN
    temp_input := i_1 & i_0;
    CASE current_state IS
    WHEN State_0 => temp_output := "0000";
    IF temp_input="00" or temp_input="01" THEN
    temp_mealy_output := "01";
    next_state <= State_1;
    ELSIF temp_input="00" or temp_input="01" THEN
    temp_mealy_output := "01";
    next_state <= State_1;
    ELSIF temp_input="00" or temp_input="01" THEN
    temp_mealy_output := "01";
    next_state <= State_1;
    ELSIF temp_input="00" or temp_input="01" THEN
    temp_mealy_output := "01";
    next_state <= State_1;
    ELSIF temp_input="00" or temp_input="01" THEN
    temp_mealy_output := "01";
    next_state <= State_1;
    ELSIF temp_input="00" or temp_input="01" THEN
    temp_mealy_output := "01";
    next_state <= State_1;

     
  • Hello, I have exactly the same problem with QFSM ver 0.52 under Win XP SP3. The VHDL code looks correct up to the "next_state_and_output_logic" process, then it appears to infinite loop while generating the first state transition. I can send an example if you wish, contact me at: larry "dot" wells "at" appcongroup "dot" com.

     
  • Stefan Duffner
    Stefan Duffner
    2012-06-20

    • status: open-accepted --> closed-fixed