When i try to generate the vhdl on this project on the windows build, the program freezes, but if you look at the vhdl generated it look likes a infinite loop. The options marked in the export options are:
-Use symbolic names for states
-Use input/output names
-Export state codes
-use std_logic_1164 package
-Write I/O description into header
The program was tested in a Windows 7 64 bits machine.The program was qsm-0.52 version.