Diff of /events/arm/armv7-ca5/events [000000] .. [6893b5] Maximize Restore

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# ARM Cortex A5 events
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# From Cortex A5 TRM
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#
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include:arm/armv7-common
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event:0x86 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_IRQ : IRQ exception taken
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event:0x87 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_FIQ : FIQ exception taken
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event:0xC0 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXT_MEM_REQ : External memory request
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event:0xC1 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXT_MEM_REQ_NC : Non-cacheable external memory request
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event:0xC2 counters:1,2,3,4,5,6 um:zero minimum:500 name:PREFETCH_LINEFILL : Linefill because of prefetch
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event:0xC3 counters:1,2,3,4,5,6 um:zero minimum:500 name:PREFETCH_LINEFILL_DROP : Prefetch linefill dropped
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event:0xC4 counters:1,2,3,4,5,6 um:zero minimum:500 name:READ_ALLOC_ENTER : Entering read allocate mode
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event:0xC5 counters:1,2,3,4,5,6 um:zero minimum:500 name:READ_ALLOC : Read allocate mode
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event:0xC9 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_SB_FULL : Data write operation that stalls the pipeline because the store buffer is full