Diff of /intel-events.php3 [b9d092] .. [abd086] Maximize Restore

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--- a/intel-events.php3
+++ b/intel-events.php3
@@ -68,45 +68,45 @@
 
 <tr><td>L2_IFETCH</td><td>	number of L2 instruction fetches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	08: (M)odified cache state
- <br/>
+ <br />
 	04: (E)xclusive cache state
- <br/>
+ <br />
 	02: (S)hared cache state
- <br/>
+ <br />
 	01: (I)nvalid cache state
- <br/>
+ <br />
 	0f: all MESI cache state
- <br/>
+ <br />
 </td>
 
 </tr>
 
 <tr><td>L2_LD</td><td>	number of L2 data loads </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	08: (M)odified cache state
- <br/>
+ <br />
 	04: (E)xclusive cache state
- <br/>
+ <br />
 	02: (S)hared cache state
- <br/>
+ <br />
 	01: (I)nvalid cache state
- <br/>
+ <br />
 	0f: all MESI cache state
- <br/>
+ <br />
 </td>
 
 </tr>
 
 <tr><td>L2_ST</td><td>	number of L2 data stores </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	08: (M)odified cache state
- <br/>
+ <br />
 	04: (E)xclusive cache state
- <br/>
+ <br />
 	02: (S)hared cache state
- <br/>
+ <br />
 	01: (I)nvalid cache state
- <br/>
+ <br />
 	0f: all MESI cache state
- <br/>
+ <br />
 </td>
 
 </tr>
@@ -133,15 +133,15 @@
 
 <tr><td>L2_RQSTS</td><td>	number of L2 requests </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	08: (M)odified cache state
- <br/>
+ <br />
 	04: (E)xclusive cache state
- <br/>
+ <br />
 	02: (S)hared cache state
- <br/>
+ <br />
 	01: (I)nvalid cache state
- <br/>
+ <br />
 	0f: all MESI cache state
- <br/>
+ <br />
 </td>
 
 </tr>
@@ -163,18 +163,18 @@
 
 <tr><td>BUS_DRDY_CLOCKS</td><td>	number of clocks DRDY is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_LOCK_CLOCKS</td><td>	number of clocks LOCK is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
@@ -186,108 +186,108 @@
 
 <tr><td>BUS_TRAN_BRD</td><td>	number of burst read transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRAN_RFO</td><td>	number of read for ownership transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRANS_WB</td><td>	number of write back transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRAN_IFETCH</td><td>	number of instruction fetch transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRAN_INVAL</td><td>	number of invalidate transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRAN_PWR</td><td>	number of partial write transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRANS_P</td><td>	number of partial transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRANS_IO</td><td>	number of I/O transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRANS_DEF</td><td>	number of deferred transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRAN_BURST</td><td>	number of burst transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRAN_ANY</td><td>	number of all transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
 
 <tr><td>BUS_TRAN_MEM</td><td>	number of memory transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
 	00: self-generated transactions
- <br/>
-	20: any transactions
- <br/>
+ <br />
+	20: any transactions
+ <br />
 </td>
 
 </tr>
@@ -364,26 +364,26 @@
 
 <tr><td>EMON_KNI_PREF_DISPATCHED</td><td>	number of KNI pre-fetch/weakly ordered insns dispatched </td><td> all</td><td> PIII</td><td>
 	00: prefetch NTA
- <br/>
+ <br />
 	01: prefetch T1
- <br/>
+ <br />
 	02: prefetch T2
- <br/>
+ <br />
 	03: weakly ordered stores
- <br/>
+ <br />
 </td>
 
 </tr>
 
 <tr><td>EMON_KNI_PREF_MISS</td><td>	number of KNI pre-fetch/weakly ordered insns that miss all caches </td><td> all</td><td> PIII</td><td>
 	00: prefetch NTA
- <br/>
+ <br />
 	01: prefetch T1
- <br/>
+ <br />
 	02: prefetch T2
- <br/>
+ <br />
 	03: weakly ordered stores
- <br/>
+ <br />
 </td>
 
 </tr>
@@ -405,18 +405,18 @@
 
 <tr><td>EMON_KNI_INST_RETIRED</td><td>	number of KNI instructions retired </td><td> all</td><td> PIII</td><td>
 	00: packed and scalar
- <br/>
+ <br />
 	01: packed
- <br/>
+ <br />
 </td>
 
 </tr>
 
 <tr><td>EMON_KNI_COMP_INST_RET</td><td>	number of KNI computation instructions retired </td><td> all</td><td> PIII</td><td>
 	00: packed and scalar
- <br/>
+ <br />
 	01: packed
- <br/>
+ <br />
 </td>
 
 </tr>
@@ -498,35 +498,35 @@
 
 <tr><td>MMX_UOPS_EXEC</td><td>	number of MMX UOPS executed </td><td> all</td><td> PII, PIII</td><td>
 	0f: mandatory
- <br/>
+ <br />
 </td>
 
 </tr>
 
 <tr><td>MMX_INSTR_TYPE_EXEC</td><td>	number of MMX packing instructions </td><td> all</td><td> PII, PIII</td><td>
 	01: MMX packed multiplies
- <br/>
+ <br />
 	02: MMX packed shifts
- <br/>
+ <br />
 	04: MMX pack operations
- <br/>
+ <br />
 	08: MMX unpack operations
- <br/>
+ <br />
 	10: MMX packed logical
- <br/>
+ <br />
 	20: MMX packed arithmetic
- <br/>
+ <br />
 	3f: All the above
- <br/>
+ <br />
 </td>
 
 </tr>
 
 <tr><td>FP_MMX_TRANS</td><td>	MMX-floating point transitions </td><td> all</td><td> PII, PIII</td><td>
 	00: MMX->float transitions
- <br/>
+ <br />
 	01: float->MMX transitions
- <br/>
+ <br />
 </td>
 
 </tr>