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1
<tr><td>CYCLES</td><td>   Cycles </td><td> 0</td><td>
2
</td>
3
4
</tr>
5
6
<tr><td>PM_1PLUS_PPC_CMPL</td><td>    one or more ppc instructions finished </td><td> 0</td><td>
7
</td>
8
9
</tr>
10
11
<tr><td>PM_1PLUS_PPC_DISP</td><td>    Cycles at least one Instr Dispatched </td><td> 3</td><td>
12
</td>
13
14
</tr>
15
16
<tr><td>PM_ANY_THRD_RUN_CYC</td><td>  One of threads in run_cycles </td><td> 0</td><td>
17
</td>
18
19
</tr>
20
21
<tr><td>PM_BR_MPRED_CMPL</td><td> Number of Branch Mispredicts </td><td> 3</td><td>
22
</td>
23
24
</tr>
25
26
<tr><td>PM_BR_TAKEN_CMPL</td><td> New event for Branch Taken </td><td> 1</td><td>
27
</td>
28
29
</tr>
30
31
<tr><td>PM_CYC</td><td>   Cycles </td><td> 0</td><td>
32
</td>
33
34
</tr>
35
36
<tr><td>PM_DATA_FROM_L2MISS</td><td>  Demand LD - L2 Miss (not L2 hit) </td><td> 1</td><td>
37
</td>
38
39
</tr>
40
41
<tr><td>PM_DATA_FROM_L3MISS</td><td>  Demand LD - L3 Miss (not L2 hit and not L3 hit) </td><td> 2</td><td>
42
</td>
43
44
</tr>
45
46
<tr><td>PM_DATA_FROM_MEM</td><td> data from Memory </td><td> 3</td><td>
47
</td>
48
49
</tr>
50
51
<tr><td>PM_DTLB_MISS</td><td> Data PTEG reload </td><td> 2</td><td>
52
</td>
53
54
</tr>
55
56
<tr><td>PM_EXT_INT</td><td>   external interrupt </td><td> 1</td><td>
57
</td>
58
59
</tr>
60
61
<tr><td>PM_FLOP</td><td>  Floating Point Operations Finished </td><td> 0</td><td>
62
</td>
63
64
</tr>
65
66
<tr><td>PM_FLUSH</td><td> Flush (any type) </td><td> 3</td><td>
67
</td>
68
69
</tr>
70
71
<tr><td>PM_GCT_NOSLOT_CYC</td><td>    No itags assigned </td><td> 0</td><td>
72
</td>
73
74
</tr>
75
76
<tr><td>PM_IERAT_MISS</td><td>    Cycles Instruction ERAT was reloaded </td><td> 0</td><td>
77
</td>
78
79
</tr>
80
81
<tr><td>PM_INST_DISP</td><td> Number of PPC Dispatched </td><td> 1</td><td>
82
</td>
83
84
</tr>
85
86
<tr><td>PM_INST_FROM_L3MISS</td><td>  A Instruction cacheline request resolved from a location that was beyond the local L3 cache </td><td> 2</td><td>
87
</td>
88
89
</tr>
90
91
<tr><td>PM_ITLB_MISS</td><td> ITLB Reloaded (always zero on POWER6) </td><td> 3</td><td>
92
</td>
93
94
</tr>
95
96
<tr><td>PM_L1_DCACHE_RELOAD_VALID</td><td>    DL1 reloaded due to Demand Load </td><td> 2</td><td>
97
</td>
98
99
</tr>
100
101
<tr><td>PM_L1_ICACHE_MISS</td><td>    Demand iCache Miss </td><td> 1</td><td>
102
</td>
103
104
</tr>
105
106
<tr><td>PM_LD_MISS_L1</td><td>    Load Missed L1 </td><td> 3</td><td>
107
</td>
108
109
</tr>
110
111
<tr><td>PM_LSU_DERAT_MISS</td><td>    DERAT Reloaded due to a DERAT miss </td><td> 1</td><td>
112
</td>
113
114
</tr>
115
116
<tr><td>PM_MRK_BR_MPRED_CMPL</td><td> Marked Branch Mispredicted </td><td> 2</td><td>
117
</td>
118
119
</tr>
120
121
<tr><td>PM_MRK_BR_TAKEN_CMPL</td><td> Marked Branch Taken completed </td><td> 0</td><td>
122
</td>
123
124
</tr>
125
126
<tr><td>PM_MRK_DATA_FROM_L2MISS</td><td>  sampled load resolved beyond L2 </td><td> 3</td><td>
127
</td>
128
129
</tr>
130
131
<tr><td>PM_MRK_DATA_FROM_L3MISS</td><td>  sampled load resolved beyond L3 </td><td> 1</td><td>
132
</td>
133
134
</tr>
135
136
<tr><td>PM_MRK_DATA_FROM_MEM</td><td> sampled load resolved from memory </td><td> 1</td><td>
137
</td>
138
139
</tr>
140
141
<tr><td>PM_MRK_DERAT_MISS</td><td>    Erat Miss (TLB Access) All page sizes </td><td> 2</td><td>
142
</td>
143
144
</tr>
145
146
<tr><td>PM_MRK_DTLB_MISS</td><td> sampled Instruction dtlb miss </td><td> 3</td><td>
147
</td>
148
149
</tr>
150
151
<tr><td>PM_MRK_INST_CMPL</td><td> Marked group complete </td><td> 3</td><td>
152
</td>
153
154
</tr>
155
156
<tr><td>PM_MRK_INST_DISP</td><td> The thread has dispatched a randomly sampled marked instruction </td><td> 0</td><td>
157
</td>
158
159
</tr>
160
161
<tr><td>PM_MRK_INST_FROM_L3MISS</td><td>  sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache </td><td> 3</td><td>
162
</td>
163
164
</tr>
165
166
<tr><td>PM_MRK_L1_ICACHE_MISS</td><td>    sampled Instruction suffered an icache Miss </td><td> 0</td><td>
167
</td>
168
169
</tr>
170
171
<tr><td>PM_MRK_L1_RELOAD_VALID</td><td>   Sampled Instruction had a data reload </td><td> 0</td><td>
172
</td>
173
174
</tr>
175
176
<tr><td>PM_MRK_LD_MISS_L1</td><td>    Marked DL1 Demand Miss </td><td> 1</td><td>
177
</td>
178
179
</tr>
180
181
<tr><td>PM_MRK_ST_CMPL</td><td>   marked store completed and sent to nest </td><td> 2</td><td>
182
</td>
183
184
</tr>
185
186
<tr><td>PM_RUN_CYC</td><td>   Run_cycles </td><td> 5</td><td>
187
</td>
188
189
</tr>
190
191
<tr><td>PM_RUN_INST_CMPL</td><td> Run_Instructions </td><td> 4</td><td>
192
</td>
193
194
</tr>
195
196
<tr><td>PM_RUN_PURR</td><td>  Run_PURR </td><td> 3</td><td>
197
</td>
198
199
</tr>
200
201
<tr><td>PM_ST_FIN</td><td>    Store Instructions Finished </td><td> 1</td><td>
202
</td>
203
204
</tr>
205
206
<tr><td>PM_ST_MISS_L1</td><td>    Store Missed L1 </td><td> 2</td><td>
207
</td>
208
209
</tr>
210
211
<tr><td>PM_TB_BIT_TRANS</td><td>  timebase event </td><td> 2</td><td>
212
</td>
213
214
</tr>
215
216
<tr><td>PM_THRD_CONC_RUN_INST</td><td>    PPC Instructions Finished when both threads in run_cycles </td><td> 2</td><td>
217
</td>
218
219
</tr>
220
221
<tr><td>PM_THRESH_EXC_1024</td><td>   Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024 </td><td> 2</td><td>
222
</td>
223
224
</tr>
225
226
<tr><td>PM_THRESH_EXC_128</td><td>    Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 128 </td><td> 3</td><td>
227
</td>
228
229
</tr>
230
231
<tr><td>PM_THRESH_EXC_2048</td><td>   Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 2048 </td><td> 3</td><td>
232
</td>
233
234
</tr>
235
236
<tr><td>PM_THRESH_EXC_256</td><td>    Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 256 </td><td> 0</td><td>
237
</td>
238
239
</tr>
240
241
<tr><td>PM_THRESH_EXC_32</td><td> Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 32 </td><td> 1</td><td>
242
</td>
243
244
</tr>
245
246
<tr><td>PM_THRESH_EXC_4096</td><td>   Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 4096 </td><td> 0</td><td>
247
</td>
248
249
</tr>
250
251
<tr><td>PM_THRESH_EXC_512</td><td>    Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512 </td><td> 1</td><td>
252
</td>
253
254
</tr>
255
256
<tr><td>PM_THRESH_EXC_64</td><td> Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64 </td><td> 2</td><td>
257
</td>
258
259
</tr>
260
261
<tr><td>PM_THRESH_MET</td><td>    Threshold exceeded </td><td> 0</td><td>
262
</td>
263
264
</tr>
265
266
<tr><td>PM_BR_2PATH</td><td>  two path branch. </td><td> 3</td><td>
267
</td>
268
269
</tr>
270
271
<tr><td>PM_BR_CMPL</td><td>   Branch Instruction completed. </td><td> 3</td><td>
272
</td>
273
274
</tr>
275
276
<tr><td>PM_BR_MRK_2PATH</td><td>  marked two path branch. </td><td> 3</td><td>
277
</td>
278
279
</tr>
280
281
<tr><td>PM_CMPLU_STALL</td><td>   Completion stall. </td><td> 0</td><td>
282
</td>
283
284
</tr>
285
286
<tr><td>PM_CMPLU_STALL_BRU</td><td>   Completion stall due to a Branch Unit. </td><td> 3</td><td>
287
</td>
288
289
</tr>
290
291
<tr><td>PM_CMPLU_STALL_BRU_CRU</td><td>   Completion stall due to IFU. </td><td> 1</td><td>
292
</td>
293
294
</tr>
295
296
<tr><td>PM_CMPLU_STALL_COQ_FULL</td><td>  Completion stall due to CO q full. </td><td> 2</td><td>
297
</td>
298
299
</tr>
300
301
<tr><td>PM_CMPLU_STALL_DCACHE_MISS</td><td>   Completion stall by Dcache miss. </td><td> 1</td><td>
302
</td>
303
304
</tr>
305
306
<tr><td>PM_CMPLU_STALL_DMISS_L21_L31</td><td> Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). </td><td> 1</td><td>
307
</td>
308
309
</tr>
310
311
<tr><td>PM_CMPLU_STALL_DMISS_L2L3</td><td>    Completion stall by Dcache miss which resolved in L2/L3. </td><td> 1</td><td>
312
</td>
313
314
</tr>
315
316
<tr><td>PM_CMPLU_STALL_DMISS_L2L3_CONFLICT</td><td>   Completion stall due to cache miss resolving in core's L2/L3 with a conflict. </td><td> 3</td><td>
317
</td>
318
319
</tr>
320
321
<tr><td>PM_CMPLU_STALL_DMISS_L3MISS</td><td>  Completion stall due to cache miss resolving missed the L3. </td><td> 3</td><td>
322
</td>
323
324
</tr>
325
326
<tr><td>PM_CMPLU_STALL_DMISS_LMEM</td><td>    Completion stall due to cache miss resolving in core's Local Memory. </td><td> 3</td><td>
327
</td>
328
329
</tr>
330
331
<tr><td>PM_CMPLU_STALL_DMISS_REMOTE</td><td>  Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). </td><td> 1</td><td>
332
</td>
333
334
</tr>
335
336
<tr><td>PM_CMPLU_STALL_ERAT_MISS</td><td> Completion stall due to LSU reject ERAT miss. </td><td> 3</td><td>
337
</td>
338
339
</tr>
340
341
<tr><td>PM_CMPLU_STALL_FLUSH</td><td> completion stall due to flush by own thread. </td><td> 2</td><td>
342
</td>
343
344
</tr>
345
346
<tr><td>PM_CMPLU_STALL_FXLONG</td><td>    Completion stall due to a long latency fixed point instruction. </td><td> 3</td><td>
347
</td>
348
349
</tr>
350
351
<tr><td>PM_CMPLU_STALL_FXU</td><td>   Completion stall due to FXU. </td><td> 1</td><td>
352
</td>
353
354
</tr>
355
356
<tr><td>PM_CMPLU_STALL_HWSYNC</td><td>    completion stall due to hwsync. </td><td> 2</td><td>
357
</td>
358
359
</tr>
360
361
<tr><td>PM_CMPLU_STALL_LOAD_FINISH</td><td>   Completion stall due to a Load finish. </td><td> 3</td><td>
362
</td>
363
364
</tr>
365
366
<tr><td>PM_CMPLU_STALL_LSU</td><td>   Completion stall by LSU instruction. </td><td> 1</td><td>
367
</td>
368
369
</tr>
370
371
<tr><td>PM_CMPLU_STALL_LWSYNC</td><td>    completion stall due to isync/lwsync. </td><td> 0</td><td>
372
</td>
373
374
</tr>
375
376
<tr><td>PM_CMPLU_STALL_MEM_ECC_DELAY</td><td> Completion stall due to mem ECC delay. </td><td> 2</td><td>
377
</td>
378
379
</tr>
380
381
<tr><td>PM_CMPLU_STALL_NTCG_FLUSH</td><td>    Completion stall due to reject (load hit store). </td><td> 1</td><td>
382
</td>
383
384
</tr>
385
386
<tr><td>PM_CMPLU_STALL_OTHER_CMPL</td><td>    Instructions core completed while this thread was stalled. </td><td> 2</td><td>
387
</td>
388
389
</tr>
390
391
<tr><td>PM_CMPLU_STALL_REJECT</td><td>    Completion stall due to LSU reject. </td><td> 3</td><td>
392
</td>
393
394
</tr>
395
396
<tr><td>PM_CMPLU_STALL_REJECT_LHS</td><td>    Completion stall due to reject (load hit store). </td><td> 1</td><td>
397
</td>
398
399
</tr>
400
401
<tr><td>PM_CMPLU_STALL_REJ_LMQ_FULL</td><td>  Completion stall due to LSU reject LMQ full. </td><td> 3</td><td>
402
</td>
403
404
</tr>
405
406
<tr><td>PM_CMPLU_STALL_SCALAR</td><td>    Completion stall due to VSU scalar instruction. </td><td> 3</td><td>
407
</td>
408
409
</tr>
410
411
<tr><td>PM_CMPLU_STALL_SCALAR_LONG</td><td>   Completion stall due to VSU scalar long latency instruction. </td><td> 1</td><td>
412
</td>
413
414
</tr>
415
416
<tr><td>PM_CMPLU_STALL_STORE</td><td> Completion stall by stores. </td><td> 1</td><td>
417
</td>
418
419
</tr>
420
421
<tr><td>PM_CMPLU_STALL_ST_FWD</td><td>    Completion stall due to store forward. </td><td> 3</td><td>
422
</td>
423
424
</tr>
425
426
<tr><td>PM_CMPLU_STALL_THRD</td><td>  Completion stall due to thread conflict. </td><td> 0</td><td>
427
</td>
428
429
</tr>
430
431
<tr><td>PM_CMPLU_STALL_VECTOR</td><td>    Completion stall due to VSU vector instruction. </td><td> 1</td><td>
432
</td>
433
434
</tr>
435
436
<tr><td>PM_CMPLU_STALL_VECTOR_LONG</td><td>   Completion stall due to VSU vector long instruction. </td><td> 3</td><td>
437
</td>
438
439
</tr>
440
441
<tr><td>PM_CMPLU_STALL_VSU</td><td>   Completion stall due to VSU instruction. </td><td> 1</td><td>
442
</td>
443
444
</tr>
445
446
<tr><td>PM_DATA_FROM_L2</td><td>  The processor's data cache was reloaded from local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
447
</td>
448
449
</tr>
450
451
<tr><td>PM_DATA_FROM_L2_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 0</td><td>
452
</td>
453
454
</tr>
455
456
<tr><td>PM_DATA_FROM_L3</td><td>  The processor's data cache was reloaded from local core's L3 due to a demand load. </td><td> 3</td><td>
457
</td>
458
459
</tr>
460
461
<tr><td>PM_DATA_FROM_L3MISS_MOD</td><td>  The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load. </td><td> 3</td><td>
462
</td>
463
464
</tr>
465
466
<tr><td>PM_DATA_FROM_L3_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
467
</td>
468
469
</tr>
470
471
<tr><td>PM_DATA_FROM_LMEM</td><td>    The processor's data cache was reloaded from the local chip's Memory due to a demand load. </td><td> 1</td><td>
472
</td>
473
474
</tr>
475
476
<tr><td>PM_DATA_FROM_MEMORY</td><td>  The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load. </td><td> 1</td><td>
477
</td>
478
479
</tr>
480
481
<tr><td>PM_DC_PREF_STREAM_STRIDED_CONF</td><td>   A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.. </td><td> 2</td><td>
482
</td>
483
484
</tr>
485
486
<tr><td>PM_GCT_NOSLOT_BR_MPRED</td><td>   Gct empty fo this thread due to branch mispred. </td><td> 3</td><td>
487
</td>
488
489
</tr>
490
491
<tr><td>PM_GCT_NOSLOT_BR_MPRED_ICMISS</td><td>    Gct empty fo this thread due to Icache Miss and branch mispred. </td><td> 3</td><td>
492
</td>
493
494
</tr>
495
496
<tr><td>PM_GCT_NOSLOT_DISP_HELD_ISSQ</td><td> Gct empty fo this thread due to dispatch hold on this thread due to Issue q full. </td><td> 1</td><td>
497
</td>
498
499
</tr>
500
501
<tr><td>PM_GCT_NOSLOT_DISP_HELD_OTHER</td><td>    Gct empty fo this thread due to dispatch hold on this thread due to sync. </td><td> 1</td><td>
502
</td>
503
504
</tr>
505
506
<tr><td>PM_GCT_NOSLOT_DISP_HELD_SRQ</td><td>  Gct empty fo this thread due to dispatch hold on this thread due to SRQ full. </td><td> 1</td><td>
507
</td>
508
509
</tr>
510
511
<tr><td>PM_GCT_NOSLOT_IC_L3MISS</td><td>  Gct empty fo this thread due to icach l3 miss. </td><td> 3</td><td>
512
</td>
513
514
</tr>
515
516
<tr><td>PM_GCT_NOSLOT_IC_MISS</td><td>    Gct empty fo this thread due to Icache Miss. </td><td> 1</td><td>
517
</td>
518
519
</tr>
520
521
<tr><td>PM_GRP_DISP</td><td>. </td><td> 2</td><td>    dispatch_success Group Dispatched</td>
522
523
</tr>
524
525
<tr><td>PM_GRP_MRK</td><td>   Instruction marked in idu. </td><td> 0</td><td>
526
</td>
527
528
</tr>
529
530
<tr><td>PM_HV_CYC</td><td>    cycles in hypervisor mode . </td><td> 1</td><td>
531
</td>
532
533
</tr>
534
535
<tr><td>PM_INST_CMPL</td><td> PPC Instructions Finished (completed). </td><td> 0</td><td>
536
</td>
537
538
</tr>
539
540
<tr><td>PM_IOPS_CMPL</td><td> IOPS Completed. </td><td> 0</td><td>
541
</td>
542
543
</tr>
544
545
<tr><td>PM_LD_CMPL</td><td>   count of Loads completed. </td><td> 0</td><td>
546
</td>
547
548
</tr>
549
550
<tr><td>PM_LD_L3MISS_PEND_CYC</td><td>    Cycles L3 miss was pending for this thread. </td><td> 0</td><td>
551
</td>
552
553
</tr>
554
555
<tr><td>PM_MRK_DATA_FROM_L2</td><td>  The processor's data cache was reloaded from local core's L2 due to a marked load. </td><td> 0</td><td>
556
</td>
557
558
</tr>
559
560
<tr><td>PM_MRK_DATA_FROM_L2MISS_CYC</td><td>  Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load. </td><td> 3</td><td>
561
</td>
562
563
</tr>
564
565
<tr><td>PM_MRK_DATA_FROM_L2_CYC</td><td>  Duration in cycles to reload from local core's L2 due to a marked load. </td><td> 3</td><td>
566
</td>
567
568
</tr>
569
570
<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L2 without conflict due to a marked load. </td><td> 0</td><td>
571
</td>
572
573
</tr>
574
575
<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC</td><td>  Duration in cycles to reload from local core's L2 without conflict due to a marked load. </td><td> 3</td><td>
576
</td>
577
578
</tr>
579
580
<tr><td>PM_MRK_DATA_FROM_L3</td><td>  The processor's data cache was reloaded from local core's L3 due to a marked load. </td><td> 3</td><td>
581
</td>
582
583
</tr>
584
585
<tr><td>PM_MRK_DATA_FROM_L3MISS_CYC</td><td>  Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load. </td><td> 1</td><td>
586
</td>
587
588
</tr>
589
590
<tr><td>PM_MRK_DATA_FROM_L3_CYC</td><td>  Duration in cycles to reload from local core's L3 due to a marked load. </td><td> 1</td><td>
591
</td>
592
593
</tr>
594
595
<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT</td><td>  The processor's data cache was reloaded from local core's L3 without conflict due to a marked load. </td><td> 0</td><td>
596
</td>
597
598
</tr>
599
600
<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC</td><td>  Duration in cycles to reload from local core's L3 without conflict due to a marked load. </td><td> 3</td><td>
601
</td>
602
603
</tr>
604
605
<tr><td>PM_MRK_DATA_FROM_LL4</td><td> The processor's data cache was reloaded from the local chip's L4 cache due to a marked load. </td><td> 0</td><td>
606
</td>
607
608
</tr>
609
610
<tr><td>PM_MRK_DATA_FROM_LL4_CYC</td><td> Duration in cycles to reload from the local chip's L4 cache due to a marked load. </td><td> 3</td><td>
611
</td>
612
613
</tr>
614
615
<tr><td>PM_MRK_DATA_FROM_LMEM</td><td>    The processor's data cache was reloaded from the local chip's Memory due to a marked load. </td><td> 1</td><td>
616
</td>
617
618
</tr>
619
620
<tr><td>PM_MRK_DATA_FROM_LMEM_CYC</td><td>    Duration in cycles to reload from the local chip's Memory due to a marked load. </td><td> 3</td><td>
621
</td>
622
623
</tr>
624
625
<tr><td>PM_MRK_DATA_FROM_MEMORY</td><td>  The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load. </td><td> 1</td><td>
626
</td>
627
628
</tr>
629
630
<tr><td>PM_MRK_DATA_FROM_MEMORY_CYC</td><td>  Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load. </td><td> 3</td><td>
631
</td>
632
633
</tr>
634
635
<tr><td>PM_MRK_GRP_CMPL</td><td>  marked instruction finished (completed). </td><td> 3</td><td>
636
</td>
637
638
</tr>
639
640
<tr><td>PM_MRK_INST_DECODED</td><td>  marked instruction decoded. Name from ISU? </td><td> 1</td><td>
641
</td>
642
643
</tr>
644
645
<tr><td>PM_MRK_L2_RC_DISP</td><td>    Marked Instruction RC dispatched in L2. </td><td> 1</td><td>
646
</td>
647
648
</tr>
649
650
<tr><td>PM_MRK_LD_MISS_L1_CYC</td><td>    Marked ld latency. </td><td> 3</td><td>
651
</td>
652
653
</tr>
654
655
<tr><td>PM_MRK_STALL_CMPLU_CYC</td><td>   Marked Group Completion Stall cycles (use edge detect to count ). </td><td> 2</td><td>
656
</td>
657
658
</tr>
659
660
<tr><td>PM_NEST_REF_CLK</td><td>  Nest reference clocks. </td><td> 2</td><td>
661
</td>
662
663
</tr>
664
665
<tr><td>PM_PMC1_OVERFLOW</td><td> Overflow from counter 1. </td><td> 1</td><td>
666
</td>
667
668
</tr>
669
670
<tr><td>PM_PMC2_OVERFLOW</td><td> Overflow from counter 2. </td><td> 2</td><td>
671
</td>
672
673
</tr>
674
675
<tr><td>PM_PMC3_OVERFLOW</td><td> Overflow from counter 3. </td><td> 3</td><td>
676
</td>
677
678
</tr>
679
680
<tr><td>PM_PMC4_OVERFLOW</td><td> Overflow from counter 4. </td><td> 0</td><td>
681
</td>
682
683
</tr>
684
685
<tr><td>PM_PMC6_OVERFLOW</td><td> Overflow from counter 6. </td><td> 2</td><td>
686
</td>
687
688
</tr>
689
690
<tr><td>PM_PPC_CMPL</td><td>  PPC Instructions Finished (completed). </td><td> 3</td><td>
691
</td>
692
693
</tr>
694
695
<tr><td>PM_THRD_ALL_RUN_CYC</td><td>  All Threads in Run_cycles (was both threads in run_cycles). </td><td> 1</td><td>
696
</td>
697
698
</tr>
699
700
<tr><td>PM_THRESH_NOT_MET</td><td>    Threshold counter did not meet threshold. </td><td> 3</td><td>
701
</td>
702
703
</tr>
704