Diff of /docs/amd-generic-events [000000] .. [93baf6] Maximize Restore

  Switch to unified view

a b/docs/amd-generic-events
1
<tr><td>DATA_CACHE_ACCESSES</td><td>  Data Cache Accesses </td><td> all</td><td>
2
</td>
3
4
</tr>
5
6
<tr><td>DATA_CACHE_MISSES</td><td>    Data Cache Misses </td><td> all</td><td>
7
  0x01: First data cache miss or streaming store to a 64B cache line
8
 <br />
9
  0x02: First streaming store to a 64B cache line
10
 <br />
11
</td>
12
13
</tr>
14
15
<tr><td>DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE</td><td>    Data Cache Refills from L2 or System </td><td> all</td><td>
16
  0x01: Fill with good data. (Final valid status is valid)
17
 <br />
18
  0x02: Early valid status turned out to be invalid
19
 <br />
20
  0x08: Fill with read data error
21
 <br />
22
</td>
23
24
</tr>
25
26
<tr><td>DATA_CACHE_REFILLS_FROM_NORTHBRIDGE</td><td>  Data Cache Refills from System </td><td> all</td><td>
27
</td>
28
29
</tr>
30
31
<tr><td>CPU_CLK_UNHALTED</td><td> CPU Clocks not Halted </td><td> all</td><td>
32
</td>
33
34
</tr>
35
36
<tr><td>INSTRUCTION_CACHE_FETCHES</td><td>    Instruction Cache Fetches </td><td> all</td><td>
37
</td>
38
39
</tr>
40
41
<tr><td>INSTRUCTION_CACHE_MISSES</td><td> Instruction Cache Misses </td><td> all</td><td>
42
</td>
43
44
</tr>
45
46
<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_L2</td><td>    Instruction Cache Refills from L2 </td><td> all</td><td>
47
</td>
48
49
</tr>
50
51
<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM</td><td>    Instruction Cache Refills from System </td><td> all</td><td>
52
</td>
53
54
</tr>
55
56
<tr><td>RETIRED_INSTRUCTIONS</td><td> Retired Instructions </td><td> all</td><td>
57
</td>
58
59
</tr>
60
61
<tr><td>RETIRED_UOPS</td><td> Retired uops </td><td> all</td><td>
62
</td>
63
64
</tr>
65
66
<tr><td>RETIRED_BRANCH_INSTRUCTIONS</td><td>  Retired Branch Instructions </td><td> all</td><td>
67
</td>
68
69
</tr>
70
71
<tr><td>RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS</td><td> Retired Mispredicted Branch Instructions </td><td> all</td><td>
72
</td>
73
74
</tr>
75
76
<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS</td><td>    Retired Taken Branch Instructions </td><td> all</td><td>
77
</td>
78
79
</tr>
80
81
<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED</td><td>   Retired Taken Branch Instructions Mispredicted </td><td> all</td><td>
82
</td>
83
84
</tr>
85
86
<tr><td>RETIRED_INDIRECT_BRANCHES_MISPREDICTED</td><td>   Retired Indirect Branches Mispredicted </td><td> all</td><td>
87
</td>
88
89
</tr>
90