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<tr><td>DATA_CACHE_ACCESSES</td><td>	Data Cache Accesses </td><td> all</td><td>
</td>

</tr>

<tr><td>DATA_CACHE_MISSES</td><td>	Data Cache Misses </td><td> all</td><td>
	0x01: First data cache miss or streaming store to a 64B cache line
 <br />
	0x02: First streaming store to a 64B cache line
 <br />
</td>

</tr>

<tr><td>DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE</td><td>	Data Cache Refills from L2 or System </td><td> all</td><td>
	0x01: Fill with good data. (Final valid status is valid)
 <br />
	0x02: Early valid status turned out to be invalid
 <br />
	0x08: Fill with read data error
 <br />
</td>

</tr>

<tr><td>DATA_CACHE_REFILLS_FROM_NORTHBRIDGE</td><td>	Data Cache Refills from System </td><td> all</td><td>
</td>

</tr>

<tr><td>CPU_CLK_UNHALTED</td><td>	CPU Clocks not Halted </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTION_CACHE_FETCHES</td><td>	Instruction Cache Fetches </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTION_CACHE_MISSES</td><td>	Instruction Cache Misses </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_L2</td><td>	Instruction Cache Refills from L2 </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM</td><td>	Instruction Cache Refills from System </td><td> all</td><td>
</td>

</tr>

<tr><td>RETIRED_INSTRUCTIONS</td><td>	Retired Instructions </td><td> all</td><td>
</td>

</tr>

<tr><td>RETIRED_UOPS</td><td>	Retired uops </td><td> all</td><td>
</td>

</tr>

<tr><td>RETIRED_BRANCH_INSTRUCTIONS</td><td>	Retired Branch Instructions </td><td> all</td><td>
</td>

</tr>

<tr><td>RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS</td><td>	Retired Mispredicted Branch Instructions </td><td> all</td><td>
</td>

</tr>

<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS</td><td>	Retired Taken Branch Instructions </td><td> all</td><td>
</td>

</tr>

<tr><td>RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED</td><td>	Retired Taken Branch Instructions Mispredicted </td><td> all</td><td>
</td>

</tr>

<tr><td>RETIRED_INDIRECT_BRANCHES_MISPREDICTED</td><td>	Retired Indirect Branches Mispredicted </td><td> all</td><td>
</td>

</tr>