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<?php require("start_page.php3"); start_page("intel-events.php3", "Intel P6 performance counter events"); ?>
<h2>Intel P6 events</h2>
<p>
This is a list of all P6-core CPU's performance counter event types. Please see the Intel Architecture 32 Family
Developer's Manual, Volume 3, Appendix A.
</p>
<table class="eventtable">
<tr class="tablehead"><td>Name</td><td>Description</td><td>Counters usable</td><td>CPU needed</td> <td>Unit mask options</td></tr>
<tr><td>CPU_CLK_UNHALTED</td><td> clocks processor is not halted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>DATA_MEM_REFS</td><td> all memory references, cachable and non </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>DCU_LINES_IN</td><td> total lines allocated in the DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>DCU_M_LINES_IN</td><td> number of M state lines allocated in DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>DCU_M_LINES_OUT</td><td> number of M lines evicted from the DCU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>DCU_MISS_OUTSTANDING</td><td> number of cycles while DCU miss outstanding </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>IFU_IFETCH</td><td> number of non/cachable instruction fetches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>IFU_IFETCH_MISS</td><td> number of instruction fetch misses </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>ITLB_MISS</td><td> number of ITLB misses </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>IFU_MEM_STALL</td><td> cycles instruction fetch pipe is stalled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>ILD_STALL</td><td> cycles instruction length decoder is stalled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>L2_IFETCH</td><td> number of L2 instruction fetches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
08: (M)odified cache state
<br />
04: (E)xclusive cache state
<br />
02: (S)hared cache state
<br />
01: (I)nvalid cache state
<br />
0f: all MESI cache state
<br />
</td>
</tr>
<tr><td>L2_LD</td><td> number of L2 data loads </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
08: (M)odified cache state
<br />
04: (E)xclusive cache state
<br />
02: (S)hared cache state
<br />
01: (I)nvalid cache state
<br />
0f: all MESI cache state
<br />
</td>
</tr>
<tr><td>L2_ST</td><td> number of L2 data stores </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
08: (M)odified cache state
<br />
04: (E)xclusive cache state
<br />
02: (S)hared cache state
<br />
01: (I)nvalid cache state
<br />
0f: all MESI cache state
<br />
</td>
</tr>
<tr><td>L2_LINES_IN</td><td> number of allocated lines in L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>L2_LINES_OUT</td><td> number of recovered lines from L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>L2_M_LINES_INM</td><td> number of modified lines allocated in L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>L2_M_LINES_OUTM</td><td> number of modified lines removed from L2 </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>L2_RQSTS</td><td> number of L2 requests </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
08: (M)odified cache state
<br />
04: (E)xclusive cache state
<br />
02: (S)hared cache state
<br />
01: (I)nvalid cache state
<br />
0f: all MESI cache state
<br />
</td>
</tr>
<tr><td>L2_ADS</td><td> number of L2 address strobes </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>L2_DBUS_BUSY</td><td> number of cycles data bus was busy </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>L2_DMUS_BUSY_RD</td><td> cycles data bus was busy in xfer from L2 to CPU </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BUS_DRDY_CLOCKS</td><td> number of clocks DRDY is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_LOCK_CLOCKS</td><td> number of clocks LOCK is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_REQ_OUTSTANDING</td><td> number of outstanding bus requests </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BUS_TRAN_BRD</td><td> number of burst read transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRAN_RFO</td><td> number of read for ownership transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRANS_WB</td><td> number of write back transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRAN_IFETCH</td><td> number of instruction fetch transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRAN_INVAL</td><td> number of invalidate transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRAN_PWR</td><td> number of partial write transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRANS_P</td><td> number of partial transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRANS_IO</td><td> number of I/O transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRANS_DEF</td><td> number of deferred transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRAN_BURST</td><td> number of burst transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRAN_ANY</td><td> number of all transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_TRAN_MEM</td><td> number of memory transactions </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
00: self-generated transactions
<br />
20: any transactions
<br />
</td>
</tr>
<tr><td>BUS_DATA_RCV</td><td> bus cycles this processor is receiving data </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BUS_BNR_DRV</td><td> bus cycles this processor is driving BNR pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BUS_HIT_DRV</td><td> bus cycles this processor is driving HIT pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BUS_HITM_DRV</td><td> bus cycles this processor is driving HITM pin </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BUS_SNOOP_STALL</td><td> cycles during bus snoop stall </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>COMP_FLOP_RET</td><td> number of computational FP operations retired </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>FLOPS</td><td> number of computational FP operations executed </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>FP_ASSIST</td><td> number of FP exceptions handled by microcode </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>MUL</td><td> number of multiplies </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>DIV</td><td> number of divides </td><td> 1</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>CYCLES_DIV_BUSY</td><td> cycles divider is busy </td><td> 0</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>LD_BLOCKS</td><td> number of store buffer blocks </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>SB_DRAINS</td><td> number of store buffer drain cycles </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>MISALIGN_MEM_REF</td><td> number of misaligned data memory references </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>EMON_KNI_PREF_DISPATCHED</td><td> number of KNI pre-fetch/weakly ordered insns dispatched </td><td> all</td><td> PIII</td><td>
00: prefetch NTA
<br />
01: prefetch T1
<br />
02: prefetch T2
<br />
03: weakly ordered stores
<br />
</td>
</tr>
<tr><td>EMON_KNI_PREF_MISS</td><td> number of KNI pre-fetch/weakly ordered insns that miss all caches </td><td> all</td><td> PIII</td><td>
00: prefetch NTA
<br />
01: prefetch T1
<br />
02: prefetch T2
<br />
03: weakly ordered stores
<br />
</td>
</tr>
<tr><td>INST_RETIRED</td><td> number of instructions retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>UOPS_RETIRED</td><td> number of UOPs retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>INST_DECODED</td><td> number of instructions decoded </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>EMON_KNI_INST_RETIRED</td><td> number of KNI instructions retired </td><td> all</td><td> PIII</td><td>
00: packed and scalar
<br />
01: packed
<br />
</td>
</tr>
<tr><td>EMON_KNI_COMP_INST_RET</td><td> number of KNI computation instructions retired </td><td> all</td><td> PIII</td><td>
00: packed and scalar
<br />
01: packed
<br />
</td>
</tr>
<tr><td>HW_INT_RX</td><td> number of hardware interrupts received </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>CYCLES_INT_MASKED</td><td> cycles interrupts are disabled </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>CYCLES_INT_PENDING_AND_MASKED</td><td> cycles interrupts are disabled with pending interrupts </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BR_INST_RETIRED</td><td> number of branch instructions retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BR_MISS_PRED_RETIRED</td><td> number of mispredicted bracnhes retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BR_TAKEN_RETIRED</td><td> number of taken branches retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BR_MISS_PRED_TAKEN_RET</td><td> number of taken mispredictions branches retired </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BR_INST_DECODED</td><td> number of branch instructions decoded </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BTB_MISSES</td><td> number of branches that miss the BTB </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BR_BOGUS</td><td> number of bogus branches </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>BACLEARS</td><td> number of times BACLEAR is asserted </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>RESOURCE_STALLS</td><td> cycles during resource related stalls </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>PARTIAL_RAT_STALLS</td><td> cycles or events for partial stalls </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>SEGMENT_REG_LOADS</td><td> number of segment register loads </td><td> all</td><td> Pentium Pro, PII, PIII</td><td>
</td>
</tr>
<tr><td>MMX_SAT_INSTR_EXEC</td><td> number of MMX saturating instructions executed </td><td> all</td><td> PII, PIII</td><td>
</td>
</tr>
<tr><td>MMX_UOPS_EXEC</td><td> number of MMX UOPS executed </td><td> all</td><td> PII, PIII</td><td>
0f: mandatory
<br />
</td>
</tr>
<tr><td>MMX_INSTR_TYPE_EXEC</td><td> number of MMX packing instructions </td><td> all</td><td> PII, PIII</td><td>
01: MMX packed multiplies
<br />
02: MMX packed shifts
<br />
04: MMX pack operations
<br />
08: MMX unpack operations
<br />
10: MMX packed logical
<br />
20: MMX packed arithmetic
<br />
3f: All the above
<br />
</td>
</tr>
<tr><td>FP_MMX_TRANS</td><td> MMX-floating point transitions </td><td> all</td><td> PII, PIII</td><td>
00: MMX->float transitions
<br />
01: float->MMX transitions
<br />
</td>
</tr>
<tr><td>MMX_ASSIST</td><td> number of EMMS instructions executed </td><td> all</td><td> PII, PIII</td><td>
</td>
</tr>
</table>
<?php require("end_page.php3"); end_page("intel-events.php3"); ?>