[28a31d]: docs / ppc-e500v2-events Maximize Restore History

Download this file

ppc-e500v2-events    406 lines (243 with data), 11.3 kB

<tr><td>CPU_CLK</td><td>	Cycles </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_INSNS</td><td>	Completed Instructions (0, 1, or 2 per cycle) </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_OPS</td><td>	Completed Micro-ops (counts 2 for load/store w/update) </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTION_FETCHES</td><td>	Instruction fetches </td><td> all</td><td>
</td>

</tr>

<tr><td>DECODED_OPS</td><td>	Micro-ops decoded </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_BRANCHES</td><td>	Branch Instructions completed </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_LOAD_OPS</td><td>	Load micro-ops completed </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_STORE_OPS</td><td>	Store micro-ops completed </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETION_REDIRECTS</td><td>	Number of completion buffer redirects </td><td> all</td><td>
</td>

</tr>

<tr><td>BRANCHES_FINISHED</td><td>	Branches finished </td><td> all</td><td>
</td>

</tr>

<tr><td>TAKEN_BRANCHES_FINISHED</td><td>	Taken branches finished </td><td> all</td><td>
</td>

</tr>

<tr><td>BIFFED_BRANCHES_FINISHED</td><td>	Biffed branches finished </td><td> all</td><td>
</td>

</tr>

<tr><td>BRANCHES_MISPREDICTED</td><td>	Branch instructions mispredicted due to direction, target, or IAB prediction </td><td> all</td><td>
</td>

</tr>

<tr><td>BRANCHES_MISPREDICTED_DIRECTION</td><td>	Branches mispredicted due to direction prediction </td><td> all</td><td>
</td>

</tr>

<tr><td>BTB_HITS</td><td>	Branches that hit in the BTB, or missed but are not taken </td><td> all</td><td>
</td>

</tr>

<tr><td>DECODE_STALLED</td><td>	Cycles the instruction buffer was not empty, but 0 instructions decoded </td><td> all</td><td>
</td>

</tr>

<tr><td>ISSUE_STALLED</td><td>	Cycles the issue buffer is not empty but 0 instructions issued  </td><td> all</td><td>
</td>

</tr>

<tr><td>BRANCH_ISSUE_STALLED</td><td>	Cycles the branch buffer is not empty but 0 instructions issued  </td><td> all</td><td>
</td>

</tr>

<tr><td>SRS0_SCHEDULE_STALLED</td><td>	Cycles SRS0 is not empty but 0 instructions scheduled  </td><td> all</td><td>
</td>

</tr>

<tr><td>SRS1_SCHEDULE_STALLED</td><td>	Cycles SRS1 is not empty but 0 instructions scheduled  </td><td> all</td><td>
</td>

</tr>

<tr><td>VRS_SCHEDULE_STALLED</td><td>	Cycles VRS is not empty but 0 instructions scheduled  </td><td> all</td><td>
</td>

</tr>

<tr><td>LRS_SCHEDULE_STALLED</td><td>	Cycles LRS is not empty but 0 instructions scheduled  </td><td> all</td><td>
</td>

</tr>

<tr><td>BRS_SCHEDULE_STALLED</td><td>	Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events  </td><td> all</td><td>
</td>

</tr>

<tr><td>TOTAL_TRANSLATED</td><td>	Total Ldst microops translated.  </td><td> all</td><td>
</td>

</tr>

<tr><td>LOADS_TRANSLATED</td><td>	Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>STORES_TRANSLATED</td><td>	Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>TOUCHES_TRANSLATED</td><td>	Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>CACHEOPS_TRANSLATED</td><td>	Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi)  </td><td> all</td><td>
</td>

</tr>

<tr><td>CACHEINHIBITED_ACCESSES_TRANSLATED</td><td>	Number of cache inhibited accesses translated  </td><td> all</td><td>
</td>

</tr>

<tr><td>GUARDED_LOADS_TRANSLATED</td><td>	Number of guarded loads translated  </td><td> all</td><td>
</td>

</tr>

<tr><td>WRITETHROUGH_STORES_TRANSLATED</td><td>	Number of write-through stores translated  </td><td> all</td><td>
</td>

</tr>

<tr><td>MISALIGNED_ACCESSES_TRANSLATED</td><td>	Number of misaligned load or store accesses translated.  </td><td> all</td><td>
</td>

</tr>

<tr><td>TOTAL_ALLOCATED_DLFB</td><td>	Total allocated to dLFB </td><td> all</td><td>
</td>

</tr>

<tr><td>LOADS_TRANSLATED_ALLOCATED_DLFB</td><td>	Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>STORES_COMPLETED_ALLOCATED_DLFB</td><td>	Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>TOUCHES_TRANSLATED_ALLOCATED_DLFB</td><td>	Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>STORES_COMPLETED</td><td>	Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>DL1_LOCKS</td><td>	Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>DL1_RELOADS</td><td>	This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason.  </td><td> all</td><td>
</td>

</tr>

<tr><td>DL1_CASTOUTS</td><td>	dL1 castouts. Does not count castouts due to DCBF.  </td><td> all</td><td>
</td>

</tr>

<tr><td>DETECTED_REPLAYS</td><td>	Times detected replay condition - Load miss with dLFB full.  </td><td> all</td><td>
</td>

</tr>

<tr><td>LOAD_MISS_QUEUE_FULL_REPLAYS</td><td>	Load miss with load queue full.  </td><td> all</td><td>
</td>

</tr>

<tr><td>LOAD_GUARDED_MISS_NOT_LAST_REPLAYS</td><td>	Load guarded miss when the load is not yet at the bottom of the completion buffer. </td><td> all</td><td>
</td>

</tr>

<tr><td>STORE_TRANSLATED_QUEUE_FULL_REPLAYS</td><td>	Translate a store when the StQ is full. </td><td> all</td><td>
</td>

</tr>

<tr><td>ADDRESS_COLLISION_REPLAYS</td><td>	Address collision. </td><td> all</td><td>
</td>

</tr>

<tr><td>DMMU_MISS_REPLAYS</td><td>	DMMU_MISS_REPLAYS : DMMU miss. </td><td> all</td><td>
</td>

</tr>

<tr><td>DMMU_BUSY_REPLAYS</td><td>	DMMU_BUSY_REPLAYS : DMMU busy. </td><td> all</td><td>
</td>

</tr>

<tr><td>SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS</td><td>	Second part of misaligned access when first part missed in cache. </td><td> all</td><td>
</td>

</tr>

<tr><td>LOAD_MISS_DLFB_FULL_CYCLES</td><td>	Cycles stalled on replay condition - Load miss with dLFB full. </td><td> all</td><td>
</td>

</tr>

<tr><td>LOAD_MISS_QUEUE_FULL_CYCLES</td><td>	Cycles stalled on replay condition - Load miss with load queue full. </td><td> all</td><td>
</td>

</tr>

<tr><td>LOAD_GUARDED_MISS_NOT_LAST_CYCLES</td><td>	Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer. </td><td> all</td><td>
</td>

</tr>

<tr><td>STORE_TRANSLATED_QUEUE_FULL_CYCLES</td><td>	Cycles stalled on replay condition - Translate a store when the StQ is full. </td><td> all</td><td>
</td>

</tr>

<tr><td>ADDRESS_COLLISION_CYCLES</td><td>	Cycles stalled on replay condition - Address collision. </td><td> all</td><td>
</td>

</tr>

<tr><td>DMMU_MISS_CYCLES</td><td>	Cycles stalled on replay condition - DMMU miss. </td><td> all</td><td>
</td>

</tr>

<tr><td>DMMU_BUSY_CYCLES</td><td>	Cycles stalled on replay condition - DMMU busy. </td><td> all</td><td>
</td>

</tr>

<tr><td>SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES</td><td>	Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache. </td><td> all</td><td>
</td>

</tr>

<tr><td>IL1_LOCKS</td><td>	Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>IL1_FETCH_RELOADS</td><td>	This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch.  </td><td> all</td><td>
</td>

</tr>

<tr><td>FETCHES</td><td>	Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)  </td><td> all</td><td>
</td>

</tr>

<tr><td>IMMU_TLB4K_RELOADS</td><td>	iMMU TLB4K reloads </td><td> all</td><td>
</td>

</tr>

<tr><td>IMMU_VSP_RELOADS</td><td>	iMMU VSP reloads </td><td> all</td><td>
</td>

</tr>

<tr><td>DMMU_TLB4K_RELOADS</td><td>	dMMU TLB4K reloads </td><td> all</td><td>
</td>

</tr>

<tr><td>DMMU_VSP_RELOADS</td><td>	dMMU VSP reloads </td><td> all</td><td>
</td>

</tr>

<tr><td>L2MMU_MISSES</td><td>	Counts iTLB/dTLB error interrupt  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_REQUESTS</td><td>	Number of master transactions. (Number of master TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_I_REQUESTS</td><td>	Number of master I-Side transactions. (Number of master I-Side TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_D_REQUESTS</td><td>	Number of master D-Side transactions. (Number of master D-Side TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_D_CASTOUT_REQUESTS</td><td>	Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_RETRIES</td><td>	Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>SNOOP_REQUESTS</td><td>	Number of externally generated snoop requests. (Counts snoop TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>SNOOP_HITS</td><td>	Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared)  </td><td> all</td><td>
</td>

</tr>

<tr><td>SNOOP_PUSHES</td><td>	Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>SNOOP_RETRIES</td><td>	Number of snoop requests retried. (Counts snoop ARTRYs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC0_OVERFLOW</td><td>	Counts the number of times PMC0[32] transitioned from 1 to 0.  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC1_OVERFLOW</td><td>	Counts the number of times PMC1[32] transitioned from 1 to 0.  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC2_OVERFLOW</td><td>	Counts the number of times PMC2[32] transitioned from 1 to 0.  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC3_OVERFLOW</td><td>	Counts the number of times PMC3[32] transitioned from 1 to 0. </td><td> all</td><td>
</td>

</tr>

<tr><td>INTERRUPTS</td><td>	Number of interrupts taken </td><td> all</td><td>
</td>

</tr>

<tr><td>EXTERNAL_INTERRUPTS</td><td>	Number of external input interrupts taken </td><td> all</td><td>
</td>

</tr>

<tr><td>CRITICAL_INTERRUPTS</td><td>	Number of critical input interrupts taken </td><td> all</td><td>
</td>

</tr>

<tr><td>SC_TRAP_INTERRUPTS</td><td>	Number of system call and trap interrupts </td><td> all</td><td>
</td>

</tr>