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<tr><td>CPU_CLK</td><td>	Cycles </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_INSNS</td><td>	Completed Instructions (0, 1, or 2 per cycle) </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTION_FETCHES</td><td>	Instruction fetches </td><td> all</td><td>
</td>

</tr>

<tr><td>PM_EVENT_TRANS</td><td>	0 to 1 translations on the pm_event input </td><td> all</td><td>
</td>

</tr>

<tr><td>PM_EVENT_CYCLES</td><td>	processor bus cycle </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_BRANCHES</td><td>	Branch Instructions completed </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_LOAD_OPS</td><td>	Load micro-ops completed </td><td> all</td><td>
</td>

</tr>

<tr><td>COMPLETED_STORE_OPS</td><td>	Store micro-ops completed </td><td> all</td><td>
</td>

</tr>

<tr><td>BRANCHES_FINISHED</td><td>	Branches finished </td><td> all</td><td>
</td>

</tr>

<tr><td>TAKEN_BRANCHES_FINISHED</td><td>	Taken branches finished </td><td> all</td><td>
</td>

</tr>

<tr><td>BRANCHES_MISPREDICTED</td><td>	Branch instructions mispredicted due to direction, target, or IAB prediction </td><td> all</td><td>
</td>

</tr>

<tr><td>DECODE_STALLED</td><td>	Cycles the instruction buffer was not empty, but 0 instructions decoded </td><td> all</td><td>
</td>

</tr>

<tr><td>ISSUE_STALLED</td><td>	Cycles the issue buffer is not empty but 0 instructions issued  </td><td> all</td><td>
</td>

</tr>

<tr><td>CACHEINHIBITED_ACCESSES_TRANSLATED</td><td>	Number of cache inhibited accesses translated  </td><td> all</td><td>
</td>

</tr>

<tr><td>FETCHES</td><td>	Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)  </td><td> all</td><td>
</td>

</tr>

<tr><td>MMU_MISSES</td><td>	Counts instruction TLB miss exceptions  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_REQUESTS</td><td>	Number of master transactions. (Number of master TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_I_REQUESTS</td><td>	Number of master I-Side transactions. (Number of master I-Side TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_D_REQUESTS</td><td>	Number of master D-Side transactions. (Number of master D-Side TSs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>BIU_MASTER_RETRIES</td><td>	Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>SNOOP_PUSHES</td><td>	Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC0_OVERFLOW</td><td>	Counts the number of times PMC0[32] transitioned from 1 to 0.  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC1_OVERFLOW</td><td>	Counts the number of times PMC1[32] transitioned from 1 to 0.  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC2_OVERFLOW</td><td>	Counts the number of times PMC2[32] transitioned from 1 to 0.  </td><td> all</td><td>
</td>

</tr>

<tr><td>PMC3_OVERFLOW</td><td>	Counts the number of times PMC3[32] transitioned from 1 to 0. </td><td> all</td><td>
</td>

</tr>

<tr><td>INTERRUPTS</td><td>	Number of interrupts taken </td><td> all</td><td>
</td>

</tr>

<tr><td>EXTERNAL_INTERRUPTS</td><td>	Number of external input interrupts taken </td><td> all</td><td>
</td>

</tr>

<tr><td>CRITICAL_INTERRUPTS</td><td>	Number of critical input interrupts taken </td><td> all</td><td>
</td>

</tr>

<tr><td>SC_TRAP_INTERRUPTS</td><td>	Number of system call and trap interrupts </td><td> all</td><td>
</td>

</tr>

<tr><td>TRANS_TBL</td><td>	Counts transitions of the TBL bit selected by PMGC0[TBSEL] </td><td> all</td><td>
</td>

</tr>

<tr><td>I_CACHE_HIT</td><td>	Number if fetches that hit in i-cache  </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTIONS_FOLDED</td><td>	Number of instructions folded </td><td> all</td><td>
</td>

</tr>

<tr><td>STALLS_COM_BUFFER</td><td>	Cycles issue stalled due to full completion buffer </td><td> all</td><td>
</td>

</tr>

<tr><td>STALLED_COMPLETION</td><td>	Cycles that completion is stalled </td><td> all</td><td>
</td>

</tr>

<tr><td>STALLED_LOAD</td><td>	Cycles that completion is stalled due to load </td><td> all</td><td>
</td>

</tr>

<tr><td>STALLED_FLOAT</td><td>	Cycles that completion is stalled due to fp instruction </td><td> all</td><td>
</td>

</tr>

<tr><td>L_S_SPACE</td><td>	Number of loads and stores to cacheable space in D cache </td><td> all</td><td>
</td>

</tr>

<tr><td>L_S_HIT</td><td>	Number of loads and stores that hit in the D cache </td><td> all</td><td>
</td>

</tr>