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<tr><td>CYCLES</td><td>	0-0 Cycles </td><td> all</td><td>
</td>

</tr>

<tr><td>INSTRUCTIONS</td><td>	1-0 Instructions graduated </td><td> all</td><td>
</td>

</tr>

<tr><td>PREDICTED_JR_31</td><td>	2-0 JR $31 (return) instructions predicted including speculative instructions </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>REDIRECT_STALLS</td><td>	3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ITLB_ACCESSES</td><td>	4-0 Instruction micro-TLB accesses </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ICACHE_ACCESSES</td><td>	6-0 Instruction cache accesses including speculative instructions </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ICACHE_MISS_STALLS</td><td>	7-0 Instruction cache miss stall cycles </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>UNCACHED_IFETCH_STALLS</td><td>	8-0 Uncached instruction fetch stall cycles </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>IFU_REPLAYS</td><td>	9-0 Replays within the IFU due to full Instruction Buffer </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>IFU_IDU_MISS_PRED_UPSTREAM_CYCLES</td><td>	11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch  </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>IFU_IDU_CLOGED_DOWNSTREAM_CYCLES</td><td>	12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>DDQ0_FULL_DR_STALLS</td><td>	13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ALCB_FULL_DR_STALLS</td><td>	14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>CLDQ_FULL_DR_STALLS</td><td>	15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ALU_EMPTY_CYCLES</td><td>	16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ALU_OPERANDS_NOT_READY_CYCLES</td><td>	17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ALU_NO_ISSUES_CYCLES</td><td>	18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ALU_BUBBLE_CYCLES</td><td>	19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SINGLE_ISSUE_CYCLES</td><td>	20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>OOO_ALU_ISSUE_CYCLES</td><td>	21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool) </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>JALR_JALR_HB_INSNS</td><td>	22-0 Graduated JALR/JALR.HB instructions </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>DCACHE_LOAD_ACCESSES</td><td>	23-0 Counts all accesses to the data cache caused by load instructions </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>DCACHE_WRITEBACKS</td><td>	24-0 Data cache writebacks </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>JTLB_DATA_ACCESSES</td><td>	25-0 Joint TLB data (non-instruction) accesses </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>LOAD_STORE_REPLAYS</td><td>	26-0 Load/store generated replays - load/store follows too closely a matching CACHEOP </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>LOAD_STORE_BLOCKED_CYCLES</td><td>	27-0 Load/store graduation blocked cycles due to CP1/2 store data not ready, SYNC/SYNCI/SC/CACHEOP at the head, or FSB/LDQ/WBB/ITU FIFO full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>L2_CACHE_WRITEBACKS</td><td>	28-0 L2 Cache Writebacks </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>L2_CACHE_MISSES</td><td>	29-0 L2 Cache Misses </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>FSB_FULL_STALLS</td><td>	30-0 Pipe stall cycles due to FSB full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>LDQ_FULL_STALLS</td><td>	31-0 Pipe stall cycles due to LDQ full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>WBB_FULL_STALLS</td><td>	32-0 Pipe stall cycles due to WBB full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>LOAD_MISS_CONSUMER_REPLAYS</td><td>	35-0 Replays following optimistic issue of instruction dependent on load which missed, counted only when the dependent instruction graduates </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>JR_NON_31_INSNS</td><td>	36-0 jr $xx (not $31) instructions graduated (at same cost as a mispredict) </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>BRANCH_INSNS</td><td>	37-0 Branch instructions graduated, excluding CP1/CP2 conditional branches </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>BRANCH_LIKELY_INSNS</td><td>	38-0 Branch likely instructions graduated including CP1 and CP2 branch likely instructions </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>COND_BRANCH_INSNS</td><td>	39-0 Conditional branches graduated </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>INTEGER_INSNS</td><td>	40-0 Integer instructions graduated including NOP, SSNOP, MOVCI, and EHB </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>LOAD_INSNS</td><td>	41-0 Loads graduated including CP1 ans CP2 loads  </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>J_JAL_INSNS</td><td>	42-0 J/JAL graduated </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>NOP_INSNS</td><td>	43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>DSP_INSNS</td><td>	44-0 DSP instructions graduated </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>DSP_BRANCH_INSNS</td><td>	45-0 DSP branch instructions graduated </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>UNCACHED_LOAD_INSNS</td><td>	46-0 Uncached loads graduated </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>EJTAG_INSN_TRIGGERS</td><td>	49-0 EJTAG instruction triggerpoints </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>CP1_BRANCH_MISPREDICTIONS</td><td>	50-0 CP1 branches mispredicted </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SC_INSNS</td><td>	51-0 SC instructions graduated </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>PREFETCH_INSNS</td><td>	52-0 Prefetch instructions graduated </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>NO_INSN_CYCLES</td><td>	53-0 No instructions graduated cycles </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ONE_INSN_CYCLES</td><td>	54-0 One instruction graduated cycles </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>GFIFO_BLOCKED_CYCLES</td><td>	55-0 GFIFO blocked cycles </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>MISPREDICTION_STALLS</td><td>	56-0 Cycles from the time of a pipe kill due to mispredict until the first new instruction graduates </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>MISPREDICTED_BRANCH_INSNS_CYCLES</td><td>	57-0 Mispredicted branch instruction graduation cycles without the delay slot  </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>EXCEPTIONS_TAKEN</td><td>	58-0 Exceptions taken </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>COREEXTEND_EVENTS</td><td>	59-0 Implementation specific CorExtend events </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>ISPRAM_EVENTS</td><td>	62-0 Implementation specific ISPRAM events </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>L2_CACHE_SINGLE_BIT_ERRORS</td><td>	63-0 Single bit errors corrected in L2 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_0</td><td>	64-0 Implementation specific system event 0 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_2</td><td>	65-0 Implementation specific system event 2 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_4</td><td>	66-0 Implementation specific system event 4 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_6</td><td>	67-0 Implementation specific system event 6 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>OCP_ALL_REQUESTS</td><td>	68-0 All OCP requests accepted </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>OCP_READ_REQUESTS</td><td>	69-0 OCP read requests accepted </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>OCP_WRITE_REQUESTS</td><td>	70-0 OCP write requests accepted </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>FSB_LESS_25_FULL</td><td>	74-0 FSB < 25% full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>LDQ_LESS_25_FULL</td><td>	75-0 LDQ < 25% full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>WBB_LESS_25_FULL</td><td>	76-0 WBB < 25% full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>JR_31_MISPREDICTIONS</td><td>	2-1 JR $31 (return) instructions mispredicted </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>JR_31_NO_PREDICTIONS</td><td>	3-1 JR $31 (return) instructions not predicted </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>ITLB_MISSES</td><td>	4-1 Instruction micro-TLB misses </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>JTLB_INSN_MISSES</td><td>	5-1 Joint TLB instruction misses </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>ICACHE_MISSES</td><td>	6-1 Instruction cache misses, includes misses from fetch-ahead and speculation </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>PDTRACE_BACK_STALLS</td><td>	8-1 PDtrace back stalls </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>KILLED_FETCH_SLOTS</td><td>	9-1 Valid fetch slots killed due to taken branches/jumps or stalling instructions </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>IFU_IDU_NO_FETCH_CYCLES</td><td>	11-1 Cycles IFU-IDU gate open but no instructions fetched by IFU </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>DDQ1_FULL_DR_STALLS</td><td>	13-1 DR stage stall cycles due to DDQ1 (AGEN out-of-order dispatch queue) full </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>AGCB_FULL_DR_STALLS</td><td>	14-1 DR stage stall cycles due to AGCB (AGEN completion buffers) full </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>IODQ_FULL_DR_STALLS</td><td>	15-1 DR stage stall cycles due to IODQ (data comming back from IO) full </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>AGEN_EMPTY_CYCLES</td><td>	16-1 DDQ1 (AGEN out-of-order dispatch queue) empty cycles </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>AGEN_OPERANDS_NOT_READY_CYCLES</td><td>	17-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>AGEN_NO_ISSUES_CYCLES</td><td>	18-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, non-issued stores blocking ready to issue loads, or non-issued CACHEOPs blocking ready to issue loads </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>AGEN_BUBBLE_CYCLES</td><td>	19-1 DDQ1 (AGEN out-of-order dispatch queue) bubbles due to MFC2 data write or cache access from FSB </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>DUAL_ISSUE_CYCLES</td><td>	20-1 Both DDQ0 (ALU out-of-order dispatch queue) and DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>OOO_AGEN_ISSUE_CYCLES</td><td>	21-1 Out-of-order AGEN issue cycles (issued instruction is not the oldest in the pool) </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>DCACHE_LINE_REFILL_REQUESTS</td><td>	22-1 Data cache line loads (line refill requests) </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>DCACHE_ACCESSES</td><td>	23-1 Data cache accesses </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>DCACHE_MISSES</td><td>	24-1 Data cache misses </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>JTLB_DATA_MISSES</td><td>	25-1 Joint TLB data (non-instruction) misses </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>VA_TRANSALTION_CORNER_CASES</td><td>	26-1 Virtual memory address translation synonyms, homonyms, and aliases (loads/stores treated as miss in the cache) </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>LOAD_STORE_NO_FILL_REQUESTS</td><td>	27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>L2_CACHE_ACCESSES</td><td>	28-1 Accesses to the L2 cache </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>L2_CACHE_MISS_CYCLES</td><td>	29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>FSB_OVER_50_FULL</td><td>	30-1 FSB > 50% full </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>LDQ_OVER_50_FULL</td><td>	31-1 LDQ > 50% full </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>WBB_OVER_50_FULL</td><td>	32-1 WBB > 50% full </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>CP1_CP2_LOAD_INSNS</td><td>	35-1 CP1/CP2 load instructions graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>MISPREDICTED_JR_31_INSNS</td><td>	36-1 jr $31 instructions graduated after mispredict </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>CP1_CP2_COND_BRANCH_INSNS</td><td>	37-1 CP1/CP2 conditional branch instructions graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>MISPREDICTED_BRANCH_LIKELY_INSNS</td><td>	38-1 Mispredicted branch likely instructions graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>MISPREDICTED_BRANCH_INSNS</td><td>	39-1 Mispredicted branches graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>FPU_INSNS</td><td>	40-1 FPU instructions graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>STORE_INSNS</td><td>	41-1 Store instructions graduated including CP1 ans CP2 stores </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>MIPS16_INSNS</td><td>	42-1 MIPS16 instructions graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>NT_MUL_DIV_INSNS</td><td>	43-1 Integer multiply/divide instructions graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>ALU_DSP_SATURATION_INSNS</td><td>	44-1 ALU-DSP graduated, result was saturated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>MDU_DSP_SATURATION_INSNS</td><td>	45-1 MDU-DSP graduated, result was saturated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>UNCACHED_STORE_INSNS</td><td>	46-1 Uncached stores graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>FAILED_SC_INSNS</td><td>	51-1 SC instructions failed </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>CACHE_HIT_PREFETCH_INSNS</td><td>	52-1 PREFETCH instructions which did nothing, because they hit in the cache </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>LOAD_MISS_INSNS</td><td>	53-1 Cacheable load instructions that miss in the cache graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>TWO_INSNS_CYCLES</td><td>	54-1 Two instructions graduated cycles </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>CP1_CP2_STORE_INSNS</td><td>	55-1 CP1/CP2 Store graduated </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>GRADUATION_REPLAYS</td><td>	58-1 Replays initiated from graduation </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>DSPRAM_EVENTS</td><td>	62-1 Implementation specific events from the DSPRAM block </td><td> 1, 3</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_1</td><td>	64-1 Implementation specific system event 1 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_3</td><td>	65-1 Implementation specific system event 3 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_5</td><td>	66-1 Implementation specific system event 5 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>SYSTEM_EVENT_7</td><td>	67-1 Implementation specific system event 7 </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>OCP_ALL_CACHEABLE_REQUESTS</td><td>	68-1 All OCP cacheable requests accepted </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>OCP_READ_CACHEABLE_REQUESTS</td><td>	69-1 OCP cacheable read request accepted </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>OCP_WRITE_CACHEABLE_REQUESTS</td><td>	70-1 OCP cacheable write request accepted </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>FSB_25_50_FULL</td><td>	74-1 FSB 25-50% full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>LDQ_25_50_FULL</td><td>	75-1 LDQ 25-50% full </td><td> 0, 2</td><td>
</td>

</tr>

<tr><td>WBB_25_50_FULL</td><td>	76-1 WBB 25-50% full </td><td> 0, 2</td><td>
</td>

</tr>