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<tr><td>CPU_CLK_UNHALTED</td><td>	Clock cycles when not halted </td><td> all</td><td>
</td>

</tr>

<tr><td>UNHALTED_REFERENCE_CYCLES</td><td>	Unhalted reference cycles </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>INST_RETIRED</td><td>	number of instructions retired </td><td> all</td><td>
</td>

</tr>

<tr><td>LLC_MISSES</td><td>	Last level cache demand requests from this core that missed the LLC </td><td> all</td><td>
	0x41: No unit mask
 <br />
</td>

</tr>

<tr><td>LLC_REFS</td><td>	Last level cache demand requests from this core </td><td> all</td><td>
	0x4f: No unit mask
 <br />
</td>

</tr>

<tr><td>BR_INST_RETIRED</td><td>	number of branch instructions retired </td><td> all</td><td>
</td>

</tr>

<tr><td>BR_MISS_PRED_RETIRED</td><td>	number of mispredicted branches retired (precise) </td><td> all</td><td>
</td>

</tr>

<tr><td>LOAD_BLOCK</td><td>	Loads that partially overlap an earlier store </td><td> all</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>SB_DRAIN</td><td>	All Store buffer stall cycles </td><td> all</td><td>
	0x07: No unit mask
 <br />
</td>

</tr>

<tr><td>MISALIGN_MEM_REF</td><td>	Misaligned store references </td><td> all</td><td>
	0x02: No unit mask
 <br />
</td>

</tr>

<tr><td>STORE_BLOCKS</td><td>	Loads delayed with at-Retirement block code </td><td> all</td><td>
	0x04: (name=at_ret) Loads delayed with at-Retirement block code
 <br />
	0x08: (name=l1d_block) Cacheable loads delayed with L1D block code
 <br />
</td>

</tr>

<tr><td>PARTIAL_ADDRESS_ALIAS</td><td>	False dependencies due to partial address aliasing </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>DTLB_LOAD_MISSES</td><td>	DTLB load misses </td><td> all</td><td>
	0x01: (name=any) DTLB load misses
 <br />
	0x02: (name=walk_completed) DTLB load miss page walks complete
 <br />
	0x04: (name=walk_cycles) DTLB load miss page walk cycles
 <br />
	0x10: (name=stlb_hit) DTLB second level hit
 <br />
	0x20: (name=pde_miss) DTLB load miss caused by low part of address
 <br />
	0x80: (name=large_walk_completed) DTLB load miss large page walks
 <br />
</td>

</tr>

<tr><td>MEM_INST_RETIRED</td><td>	Memory instructions retired above 0 clocks (Precise Event) </td><td> all</td><td>
	0x01: (name=loads) Instructions retired which contains a load (Precise Event)
 <br />
	0x02: (name=stores) Instructions retired which contains a store (Precise Event)
 <br />
</td>

</tr>

<tr><td>MEM_STORE_RETIRED</td><td>	Retired stores that miss the DTLB (Precise Event) </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>UOPS_ISSUED</td><td>	Uops issued </td><td> all</td><td>
	0x01: (name=any) Uops issued
 <br />
	0x02: (name=fused) Fused Uops issued
 <br />
</td>

</tr>

<tr><td>MEM_UNCORE_RETIRED</td><td>	Load instructions retired that HIT modified data in sibling core (Precise Event) </td><td> all</td><td>
	0x02: (name=local_hitm) Load instructions retired that HIT modified data in sibling core (Precise Event)
 <br />
	0x04: (name=remote_hitm) Retired loads that hit remote socket in modified state (Precise Event)
 <br />
	0x08: (name=local_dram_and_remote_cache_hit) Load instructions retired local dram and remote cache HIT data sources (Precise Event)
 <br />
	0x10: (name=remote_dram) Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)
 <br />
	0x80: (name=uncacheable) Load instructions retired IO (Precise Event)
 <br />
</td>

</tr>

<tr><td>FP_COMP_OPS_EXE</td><td>	MMX Uops </td><td> all</td><td>
	0x01: (name=x87) Computational floating-point operations executed
 <br />
	0x02: (name=mmx) MMX Uops
 <br />
	0x04: (name=sse_fp) SSE and SSE2 FP Uops
 <br />
	0x08: (name=sse2_integer) SSE2 integer Uops
 <br />
	0x10: (name=sse_fp_packed) SSE FP packed Uops
 <br />
	0x20: (name=sse_fp_scalar) SSE FP scalar Uops
 <br />
	0x40: (name=sse_single_precision) SSE* FP single precision Uops
 <br />
	0x80: (name=sse_double_precision) SSE* FP double precision Uops
 <br />
</td>

</tr>

<tr><td>SIMD_INT_128</td><td>	128 bit SIMD integer pack operations </td><td> all</td><td>
	0x01: (name=packed_mpy) 128 bit SIMD integer multiply operations
 <br />
	0x02: (name=packed_shift) 128 bit SIMD integer shift operations
 <br />
	0x04: (name=pack) 128 bit SIMD integer pack operations
 <br />
	0x08: (name=unpack) 128 bit SIMD integer unpack operations
 <br />
	0x10: (name=packed_logical) 128 bit SIMD integer logical operations
 <br />
	0x20: (name=packed_arith) 128 bit SIMD integer arithmetic operations
 <br />
	0x40: (name=shuffle_move) 128 bit SIMD integer shuffle/move operations
 <br />
</td>

</tr>

<tr><td>LOAD_DISPATCH</td><td>	All loads dispatched </td><td> all</td><td>
	0x01: (name=rs) Loads dispatched that bypass the MOB
 <br />
	0x02: (name=rs_delayed) Loads dispatched from stage 305
 <br />
	0x04: (name=mob) Loads dispatched from the MOB
 <br />
	0x07: (name=any) All loads dispatched
 <br />
</td>

</tr>

<tr><td>ARITH</td><td>	Cycles the divider is busy </td><td> all</td><td>
	0x01: (name=cycles_div_busy) Cycles the divider is busy
 <br />
	0x02: (name=mul) Multiply operations executed
 <br />
</td>

</tr>

<tr><td>INST_QUEUE_WRITES</td><td>	Instructions written to instruction queue. </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>INST_DECODED</td><td>	Instructions that must be decoded by decoder 0 </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>TWO_UOP_INSTS_DECODED</td><td>	Two Uop instructions decoded </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>INST_QUEUE_WRITE_CYCLES</td><td>	Cycles instructions are written to the instruction queue </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>LSD_OVERFLOW</td><td>	Loops that can't stream from the instruction queue </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>L2_RQSTS</td><td>	L2 instruction fetch hits </td><td> all</td><td>
	0x01: (name=ld_hit) L2 load hits
 <br />
	0x02: (name=ld_miss) L2 load misses
 <br />
	0x03: (name=loads) L2 requests
 <br />
	0x04: (name=rfo_hit) L2 RFO hits
 <br />
	0x08: (name=rfo_miss) L2 RFO misses
 <br />
	0x0c: (name=rfos) L2 RFO requests
 <br />
	0x10: (name=ifetch_hit) L2 instruction fetch hits
 <br />
	0x20: (name=ifetch_miss) L2 instruction fetch misses
 <br />
	0x30: (name=ifetches) L2 instruction fetches
 <br />
	0x40: (name=prefetch_hit) L2 prefetch hits
 <br />
	0x80: (name=prefetch_miss) L2 prefetch misses
 <br />
	0xaa: (name=miss) All L2 misses
 <br />
	0xc0: (name=prefetches) All L2 prefetches
 <br />
	0xff: (name=references) All L2 requests
 <br />
</td>

</tr>

<tr><td>L2_DATA_RQSTS</td><td>	All L2 data requests </td><td> all</td><td>
	0x01: (name=demand_i_state) L2 data demand loads in I state (misses)
 <br />
	0x02: (name=demand_s_state) L2 data demand loads in S state
 <br />
	0x04: (name=demand_e_state) L2 data demand loads in E state
 <br />
	0x08: (name=demand_m_state) L2 data demand loads in M state
 <br />
	0x0f: (name=demand_mesi) L2 data demand requests
 <br />
	0x10: (name=prefetch_i_state) L2 data prefetches in the I state (misses)
 <br />
	0x20: (name=prefetch_s_state) L2 data prefetches in the S state
 <br />
	0x40: (name=prefetch_e_state) L2 data prefetches in E state
 <br />
	0x80: (name=prefetch_m_state) L2 data prefetches in M state
 <br />
	0xf0: (name=prefetch_mesi) All L2 data prefetches
 <br />
	0xff: (name=any) All L2 data requests
 <br />
</td>

</tr>

<tr><td>L2_WRITE</td><td>	L2 demand lock RFOs in E state </td><td> all</td><td>
	0x01: (name=rfo_i_state) L2 demand store RFOs in I state (misses)
 <br />
	0x02: (name=rfo_s_state) L2 demand store RFOs in S state
 <br />
	0x08: (name=rfo_m_state) L2 demand store RFOs in M state
 <br />
	0x0e: (name=rfo_hit) All L2 demand store RFOs that hit the cache
 <br />
	0x0f: (name=rfo_mesi) All L2 demand store RFOs
 <br />
	0x10: (name=lock_i_state) L2 demand lock RFOs in I state (misses)
 <br />
	0x20: (name=lock_s_state) L2 demand lock RFOs in S state
 <br />
	0x40: (name=lock_e_state) L2 demand lock RFOs in E state
 <br />
	0x80: (name=lock_m_state) L2 demand lock RFOs in M state
 <br />
	0xe0: (name=lock_hit) All demand L2 lock RFOs that hit the cache
 <br />
	0xf0: (name=lock_mesi) All demand L2 lock RFOs
 <br />
</td>

</tr>

<tr><td>L1D_WB_L2</td><td>	L1 writebacks to L2 in E state </td><td> all</td><td>
	0x01: (name=i_state) L1 writebacks to L2 in I state (misses)
 <br />
	0x02: (name=s_state) L1 writebacks to L2 in S state
 <br />
	0x04: (name=e_state) L1 writebacks to L2 in E state
 <br />
	0x08: (name=m_state) L1 writebacks to L2 in M state
 <br />
	0x0f: (name=mesi) All L1 writebacks to L2
 <br />
</td>

</tr>

<tr><td>LONGEST_LAT_CACHE</td><td>	Longest latency cache miss </td><td> all</td><td>
	0x01: (name=miss) Longest latency cache miss
 <br />
	0x02: (name=reference) Longest latency cache reference
 <br />
</td>

</tr>

<tr><td>CPU_CLK_UNHALTED</td><td>	Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) </td><td> all</td><td>
	0x00: (name=thread_p) Cycles when thread is not halted (programmable counter)
 <br />
	0x01: (name=ref_p) Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
 <br />
</td>

</tr>

<tr><td>DTLB_MISSES</td><td>	DTLB misses </td><td> all</td><td>
	0x01: (name=any) DTLB misses
 <br />
	0x02: (name=walk_completed) DTLB miss page walks
 <br />
	0x04: (name=walk_cycles) DTLB miss page walk cycles
 <br />
	0x10: (name=stlb_hit) DTLB first level misses but second level hit
 <br />
	0x20: (name=pde_miss) DTLB misses casued by low part of address
 <br />
	0x80: (name=large_walk_completed) DTLB miss large page walks
 <br />
</td>

</tr>

<tr><td>LOAD_HIT_PRE</td><td>	Load operations conflicting with software prefetches </td><td> 0, 1</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>L1D_PREFETCH</td><td>	L1D hardware prefetch misses </td><td> 0, 1</td><td>
	0x01: (name=requests) L1D hardware prefetch requests
 <br />
	0x02: (name=miss) L1D hardware prefetch misses
 <br />
	0x04: (name=triggers) L1D hardware prefetch requests triggered
 <br />
</td>

</tr>

<tr><td>EPT</td><td>	Extended Page Table walk cycles </td><td> all</td><td>
	0x10: No unit mask
 <br />
</td>

</tr>

<tr><td>L1D</td><td>	L1D cache lines replaced in M state  </td><td> 0, 1</td><td>
	0x01: (name=repl) L1 data cache lines allocated
 <br />
	0x02: (name=m_repl) L1D cache lines allocated in the M state
 <br />
	0x04: (name=m_evict) L1D cache lines replaced in M state
 <br />
	0x08: (name=m_snoop_evict) L1D snoop eviction of cache lines in M state
 <br />
</td>

</tr>

<tr><td>L1D_CACHE_PREFETCH_LOCK_FB_HIT</td><td>	L1D prefetch load lock accepted in fill buffer </td><td> 0, 1</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>OFFCORE_REQUESTS_OUTSTANDING</td><td>	Outstanding offcore reads </td><td> 0</td><td>
	0x01: (name=demand_read_data) Outstanding offcore demand data reads
 <br />
	0x02: (name=demand_read_code) Outstanding offcore demand code reads
 <br />
	0x04: (name=demand_rfo) Outstanding offcore demand RFOs
 <br />
	0x08: (name=any_read) Outstanding offcore reads
 <br />
</td>

</tr>

<tr><td>CACHE_LOCK_CYCLES</td><td>	Cycles L1D locked </td><td> 0, 1</td><td>
	0x01: (name=l1d_l2) Cycles L1D and L2 locked
 <br />
	0x02: (name=l1d) Cycles L1D locked
 <br />
</td>

</tr>

<tr><td>IO_TRANSACTIONS</td><td>	I/O transactions </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>L1I</td><td>	L1I instruction fetch stall cycles </td><td> all</td><td>
	0x01: (name=hits) L1I instruction fetch hits
 <br />
	0x02: (name=misses) L1I instruction fetch misses
 <br />
	0x03: (name=reads) L1I Instruction fetches
 <br />
	0x04: (name=cycles_stalled) L1I instruction fetch stall cycles
 <br />
</td>

</tr>

<tr><td>LARGE_ITLB</td><td>	Large ITLB hit </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>ITLB_MISSES</td><td>	ITLB miss </td><td> all</td><td>
	0x01: (name=any) ITLB miss
 <br />
	0x02: (name=walk_completed) ITLB miss page walks
 <br />
	0x04: (name=walk_cycles) ITLB miss page walk cycles
 <br />
	0x80: (name=large_walk_completed) ITLB miss large page walks
 <br />
</td>

</tr>

<tr><td>ILD_STALL</td><td>	Any Instruction Length Decoder stall cycles </td><td> all</td><td>
	0x01: (name=lcp) Length Change Prefix stall cycles
 <br />
	0x02: (name=mru) Stall cycles due to BPU MRU bypass
 <br />
	0x04: (name=iq_full) Instruction Queue full stall cycles
 <br />
	0x08: (name=regen) Regen stall cycles
 <br />
	0x0f: (name=any) Any Instruction Length Decoder stall cycles
 <br />
</td>

</tr>

<tr><td>BR_INST_EXEC</td><td>	Branch instructions executed </td><td> all</td><td>
	0x01: (name=cond) Conditional branch instructions executed
 <br />
	0x02: (name=direct) Unconditional branches executed
 <br />
	0x04: (name=indirect_non_call) Indirect non call branches executed
 <br />
	0x07: (name=non_calls) All non call branches executed
 <br />
	0x08: (name=return_near) Indirect return branches executed
 <br />
	0x10: (name=direct_near_call) Unconditional call branches executed
 <br />
	0x20: (name=indirect_near_call) Indirect call branches executed
 <br />
	0x30: (name=near_calls) Call branches executed
 <br />
	0x40: (name=taken) Taken branches executed
 <br />
	0x7f: (name=any) Branch instructions executed
 <br />
</td>

</tr>

<tr><td>BR_MISP_EXEC</td><td>	Mispredicted branches executed </td><td> all</td><td>
	0x01: (name=cond) Mispredicted conditional branches executed
 <br />
	0x02: (name=direct) Mispredicted unconditional branches executed
 <br />
	0x04: (name=indirect_non_call) Mispredicted indirect non call branches executed
 <br />
	0x07: (name=non_calls) Mispredicted non call branches executed
 <br />
	0x08: (name=return_near) Mispredicted return branches executed
 <br />
	0x10: (name=direct_near_call) Mispredicted non call branches executed
 <br />
	0x20: (name=indirect_near_call) Mispredicted indirect call branches executed
 <br />
	0x30: (name=near_calls) Mispredicted call branches executed
 <br />
	0x40: (name=taken) Mispredicted taken branches executed
 <br />
	0x7f: (name=any) Mispredicted branches executed
 <br />
</td>

</tr>

<tr><td>RESOURCE_STALLS</td><td>	Resource related stall cycles </td><td> all</td><td>
	0x01: (name=any) Resource related stall cycles
 <br />
	0x02: (name=load) Load buffer stall cycles
 <br />
	0x04: (name=rs_full) Reservation Station full stall cycles
 <br />
	0x08: (name=store) Store buffer stall cycles
 <br />
	0x10: (name=rob_full) ROB full stall cycles
 <br />
	0x20: (name=fpcw) FPU control word write stall cycles
 <br />
	0x40: (name=mxcsr) MXCSR rename stall cycles
 <br />
	0x80: (name=other) Other Resource related stall cycles
 <br />
</td>

</tr>

<tr><td>MACRO_INSTS</td><td>	Macro-fused instructions decoded </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>BACLEAR_FORCE_IQ</td><td>	Instruction queue forced BACLEAR </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>LSD</td><td>	Cycles when uops were delivered by the LSD </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>ITLB_FLUSH</td><td>	ITLB flushes </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>OFFCORE_REQUESTS</td><td>	All offcore requests </td><td> all</td><td>
	0x01: (name=demand_read_data) Offcore demand data read requests
 <br />
	0x02: (name=demand_read_code) Offcore demand code read requests
 <br />
	0x04: (name=demand_rfo) Offcore demand RFO requests
 <br />
	0x08: (name=any_read) Offcore read requests
 <br />
	0x10: (name=any_rfo) Offcore RFO requests
 <br />
	0x40: (name=l1d_writeback) Offcore L1 data cache writebacks
 <br />
	0x80: (name=any) All offcore requests
 <br />
</td>

</tr>

<tr><td>UOPS_EXECUTED</td><td>	Cycles Uops executed on any port (core count) </td><td> all</td><td>
	0x01: (name=port0) Uops executed on port 0
 <br />
	0x02: (name=port1) Uops executed on port 1
 <br />
	0x04: (name=port2_core) Uops executed on port 2 (core count)
 <br />
	0x08: (name=port3_core) Uops executed on port 3 (core count)
 <br />
	0x10: (name=port4_core) Uops executed on port 4 (core count)
 <br />
	0x1f: (name=core_active_cycles_no_port5) Cycles Uops executed on ports 0-4 (core count)
 <br />
	0x20: (name=port5) Uops executed on port 5
 <br />
	0x3f: (name=core_active_cycles) Cycles Uops executed on any port (core count)
 <br />
	0x40: (name=port015) Uops issued on ports 0, 1 or 5
 <br />
	0x80: (name=port234_core) Uops issued on ports 2, 3 or 4
 <br />
</td>

</tr>

<tr><td>OFFCORE_REQUESTS_SQ_FULL</td><td>	Offcore requests blocked due to Super Queue full </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>SNOOPQ_REQUESTS_OUTSTANDING</td><td>	Outstanding snoop code requests </td><td> 0</td><td>
	0x01: (name=data) Outstanding snoop data requests
 <br />
	0x02: (name=invalidate) Outstanding snoop invalidate requests
 <br />
	0x04: (name=code) Outstanding snoop code requests
 <br />
</td>

</tr>

<tr><td>SNOOPQ_REQUESTS</td><td>	Snoop code requests </td><td> all</td><td>
	0x01: (name=data) Snoop data requests
 <br />
	0x02: (name=invalidate) Snoop invalidate requests
 <br />
	0x04: (name=code) Snoop code requests
 <br />
</td>

</tr>

<tr><td>OFFCORE_RESPONSE_ANY_DATA</td><td>	REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM </td><td> 2</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>SNOOP_RESPONSE</td><td>	Thread responded HIT to snoop </td><td> all</td><td>
	0x01: (name=hit) Thread responded HIT to snoop
 <br />
	0x02: (name=hite) Thread responded HITE to snoop
 <br />
	0x04: (name=hitm) Thread responded HITM to snoop
 <br />
</td>

</tr>

<tr><td>OFFCORE_RESPONSE_ANY_DATA</td><td>	REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM </td><td> 1</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>INST_RETIRED</td><td>	Instructions retired (Programmable counter and Precise Event) </td><td> all</td><td>
	0x01: (name=any_p) Instructions retired (Programmable counter and Precise Event)
 <br />
	0x02: (name=x87) Retired floating-point operations (Precise Event)
 <br />
	0x04: (name=mmx) Retired MMX instructions (Precise Event)
 <br />
</td>

</tr>

<tr><td>UOPS_RETIRED</td><td>	Cycles Uops are being retired </td><td> all</td><td>
	0x01: (name=active_cycles) Cycles Uops are being retired
 <br />
	0x02: (name=retire_slots) Retirement slots used (Precise Event)
 <br />
	0x04: (name=macro_fused) Macro-fused Uops retired (Precise Event)
 <br />
</td>

</tr>

<tr><td>MACHINE_CLEARS</td><td>	Cycles machine clear asserted </td><td> all</td><td>
	0x01: (name=cycles) Cycles machine clear asserted
 <br />
	0x02: (name=mem_order) Execution pipeline restart due to Memory ordering conflicts
 <br />
	0x04: (name=smc) Self-Modifying Code detected
 <br />
</td>

</tr>

<tr><td>BR_INST_RETIRED</td><td>	Retired branch instructions (Precise Event) </td><td> all</td><td>
	0x01: (name=conditional) Retired conditional branch instructions (Precise Event)
 <br />
	0x02: (name=near_call) Retired near call instructions (Precise Event)
 <br />
	0x04: (name=all_branches) Retired branch instructions (Precise Event)
 <br />
</td>

</tr>

<tr><td>BR_MISP_RETIRED</td><td>	Mispredicted retired branch instructions (Precise Event) </td><td> all</td><td>
	0x01: (name=conditional) Mispredicted conditional retired branches (Precise Event)
 <br />
	0x02: (name=near_call) Mispredicted near retired calls (Precise Event)
 <br />
	0x04: (name=all_branches) Mispredicted retired branch instructions (Precise Event)
 <br />
</td>

</tr>

<tr><td>SSEX_UOPS_RETIRED</td><td>	SIMD Packed-Double Uops retired (Precise Event) </td><td> all</td><td>
	0x01: (name=packed_single) SIMD Packed-Single Uops retired (Precise Event)
 <br />
	0x02: (name=scalar_single) SIMD Scalar-Single Uops retired (Precise Event)
 <br />
	0x04: (name=packed_double) SIMD Packed-Double Uops retired (Precise Event)
 <br />
	0x08: (name=scalar_double) SIMD Scalar-Double Uops retired (Precise Event)
 <br />
	0x10: (name=vector_integer) SIMD Vector Integer Uops retired (Precise Event)
 <br />
</td>

</tr>

<tr><td>ITLB_MISS_RETIRED</td><td>	Retired instructions that missed the ITLB (Precise Event) </td><td> all</td><td>
	0x20: No unit mask
 <br />
</td>

</tr>

<tr><td>MEM_LOAD_RETIRED</td><td>	Retired loads that miss the DTLB (Precise Event) </td><td> all</td><td>
	0x01: (name=l1d_hit) Retired loads that hit the L1 data cache (Precise Event)
 <br />
	0x02: (name=l2_hit) Retired loads that hit the L2 cache (Precise Event)
 <br />
	0x04: (name=llc_unshared_hit) Retired loads that hit valid versions in the LLC cache (Precise Event)
 <br />
	0x08: (name=other_core_l2_hit_hitm) Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
 <br />
	0x10: (name=llc_miss) Retired loads that miss the LLC cache (Precise Event)
 <br />
	0x40: (name=hit_lfb) Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
 <br />
	0x80: (name=dtlb_miss) Retired loads that miss the DTLB (Precise Event)
 <br />
</td>

</tr>

<tr><td>FP_MMX_TRANS</td><td>	All Floating Point to and from MMX transitions </td><td> all</td><td>
	0x01: (name=to_fp) Transitions from MMX to Floating Point instructions
 <br />
	0x02: (name=to_mmx) Transitions from Floating Point to MMX instructions
 <br />
	0x03: (name=any) All Floating Point to and from MMX transitions
 <br />
</td>

</tr>

<tr><td>MACRO_INSTS</td><td>	Instructions decoded </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>UOPS_DECODED</td><td>	Stack pointer instructions decoded </td><td> all</td><td>
	0x01: (name=stall_cycles) Cycles no Uops are decoded
 <br />
	0x02: (name=ms_cycles_active) Uops decoded by Microcode Sequencer
 <br />
	0x04: (name=esp_folding) Stack pointer instructions decoded
 <br />
	0x08: (name=esp_sync) Stack pointer sync operations
 <br />
</td>

</tr>

<tr><td>RAT_STALLS</td><td>	All RAT stall cycles </td><td> all</td><td>
	0x01: (name=flags) Flag stall cycles
 <br />
	0x02: (name=registers) Partial register stall cycles
 <br />
	0x04: (name=rob_read_port) ROB read port stalls cycles
 <br />
	0x08: (name=scoreboard) Scoreboard stall cycles
 <br />
	0x0f: (name=any) All RAT stall cycles
 <br />
</td>

</tr>

<tr><td>SEG_RENAME_STALLS</td><td>	Segment rename stall cycles </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>ES_REG_RENAMES</td><td>	ES segment renames </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>UOP_UNFUSION</td><td>	Uop unfusions due to FP exceptions </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>BR_INST_DECODED</td><td>	Branch instructions decoded </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>BPU_MISSED_CALL_RET</td><td>	Branch prediction unit missed call or return </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>BACLEAR</td><td>	BACLEAR asserted with bad target address </td><td> all</td><td>
	0x01: (name=clear) BACLEAR asserted, regardless of cause
 <br />
	0x02: (name=bad_target) BACLEAR asserted with bad target address
 <br />
</td>

</tr>

<tr><td>BPU_CLEARS</td><td>	Early Branch Prediction Unit clears </td><td> all</td><td>
	0x01: (name=early) Early Branch Prediction Unit clears
 <br />
	0x02: (name=late) Late Branch Prediction Unit clears
 <br />
</td>

</tr>

<tr><td>L2_TRANSACTIONS</td><td>	All L2 transactions </td><td> all</td><td>
	0x01: (name=load) L2 Load transactions
 <br />
	0x02: (name=rfo) L2 RFO transactions
 <br />
	0x04: (name=ifetch) L2 instruction fetch transactions
 <br />
	0x08: (name=prefetch) L2 prefetch transactions
 <br />
	0x10: (name=l1d_wb) L1D writeback to L2 transactions
 <br />
	0x20: (name=fill) L2 fill transactions
 <br />
	0x40: (name=wb) L2 writeback to LLC transactions
 <br />
	0x80: (name=any) All L2 transactions
 <br />
</td>

</tr>

<tr><td>L2_LINES_IN</td><td>	L2 lines alloacated </td><td> all</td><td>
	0x02: (name=s_state) L2 lines allocated in the S state
 <br />
	0x04: (name=e_state) L2 lines allocated in the E state
 <br />
	0x07: (name=any) L2 lines alloacated
 <br />
</td>

</tr>

<tr><td>L2_LINES_OUT</td><td>	L2 lines evicted </td><td> all</td><td>
	0x01: (name=demand_clean) L2 lines evicted by a demand request
 <br />
	0x02: (name=demand_dirty) L2 modified lines evicted by a demand request
 <br />
	0x04: (name=prefetch_clean) L2 lines evicted by a prefetch request
 <br />
	0x08: (name=prefetch_dirty) L2 modified lines evicted by a prefetch request
 <br />
	0x0f: (name=any) L2 lines evicted
 <br />
</td>

</tr>

<tr><td>SQ_MISC</td><td>	Super Queue LRU hints sent to LLC </td><td> all</td><td>
	0x04: (name=lru_hints) Super Queue LRU hints sent to LLC
 <br />
	0x10: (name=split_lock) Super Queue lock splits across a cache line
 <br />
</td>

</tr>

<tr><td>SQ_FULL_STALL_CYCLES</td><td>	Super Queue full stall cycles </td><td> all</td><td>
	0x01: No unit mask
 <br />
</td>

</tr>

<tr><td>FP_ASSIST</td><td>	X87 Floating point assists (Precise Event) </td><td> all</td><td>
	0x01: (name=all) X87 Floating point assists (Precise Event)
 <br />
	0x02: (name=output) X87 Floating point assists for invalid output value (Precise Event)
 <br />
	0x04: (name=input) X87 Floating poiint assists for invalid input value (Precise Event)
 <br />
</td>

</tr>

<tr><td>SIMD_INT_64</td><td>	SIMD integer 64 bit pack operations </td><td> all</td><td>
	0x01: (name=packed_mpy) SIMD integer 64 bit packed multiply operations
 <br />
	0x02: (name=packed_shift) SIMD integer 64 bit shift operations
 <br />
	0x04: (name=pack) SIMD integer 64 bit pack operations
 <br />
	0x08: (name=unpack) SIMD integer 64 bit unpack operations
 <br />
	0x10: (name=packed_logical) SIMD integer 64 bit logical operations
 <br />
	0x20: (name=packed_arith) SIMD integer 64 bit arithmetic operations
 <br />
	0x40: (name=shuffle_move) SIMD integer 64 bit shuffle/move operations
 <br />
</td>

</tr>