--- a/docs/intel-ivybridge-events
+++ b/docs/intel-ivybridge-events
@@ -40,681 +40,681 @@
 </tr>
 
 <tr><td>ld_blocks</td><td>	Blocked loads </td><td> all</td><td>
-	0x02: store_forward loads blocked by overlapping with store buffer that cannot be forwarded
+	0x02: (name=store_forward) loads blocked by overlapping with store buffer that cannot be forwarded
  <br />
 </td>
 
 </tr>
 
 <tr><td>misalign_mem_ref</td><td>	Misaligned memory references </td><td> all</td><td>
-	0x01: loads Speculative cache line split load uops dispatched to L1 cache
- <br />
-	0x02: stores Speculative cache line split STA uops dispatched to L1 cache
+	0x01: (name=loads) Speculative cache line split load uops dispatched to L1 cache
+ <br />
+	0x02: (name=stores) Speculative cache line split STA uops dispatched to L1 cache
  <br />
 </td>
 
 </tr>
 
 <tr><td>ld_blocks_partial</td><td>	Partial loads </td><td> all</td><td>
-	0x01: address_alias False dependencies in MOB due to partial compare on address
+	0x01: (name=address_alias) False dependencies in MOB due to partial compare on address
  <br />
 </td>
 
 </tr>
 
 <tr><td>dtlb_load_misses</td><td>	D-TLB misses </td><td> all</td><td>
-	0x81: demand_ld_miss_causes_a_walk Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.
- <br />
-	0x82: demand_ld_walk_completed Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
- <br />
-	0x84: demand_ld_walk_duration Demand load cycles page miss handler (PMH) is busy with this walk.
+	0x81: (name=demand_ld_miss_causes_a_walk) Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.
+ <br />
+	0x82: (name=demand_ld_walk_completed) Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.
+ <br />
+	0x84: (name=demand_ld_walk_duration) Demand load cycles page miss handler (PMH) is busy with this walk.
  <br />
 </td>
 
 </tr>
 
 <tr><td>int_misc</td><td>	Instruction decoder events </td><td> all</td><td>
-	0x03: recovery_cycles Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) (extra: cmask=1)
- <br />
-	0x03: recovery_stalls_count Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...) (extra: edge cmask=1)
- <br />
-</td>
-
-</tr>
-
-<tr><td>uops_issued</td><td>	Uops issued </td><td> 0, 1, 2, 3</td><td>
-	0x01: any Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)
- <br />
-	0x01: stall_cycles Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread (extra: inv cmask=1)
- <br />
-	0x01: core_stall_cycles Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads (extra: inv cmask=1)
- <br />
-	0x10: flags_merge Number of flags-merge uops being allocated.
- <br />
-	0x20: slow_lea Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
- <br />
-	0x40: single_mul Number of Multiply packed/scalar single precision uops allocated
+	0x03: (name=recovery_cycles) Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)
+ <br />
+	0x03: (name=recovery_stalls_count) Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...)
+ <br />
+</td>
+
+</tr>
+
+<tr><td>uops_issued</td><td>	Uops issued </td><td> all</td><td>
+	0x01: (name=any) Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)
+ <br />
+	0x01: (name=stall_cycles) Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread
+ <br />
+	0x01: (name=core_stall_cycles) Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads
+ <br />
+	0x10: (name=flags_merge) Number of flags-merge uops being allocated.
+ <br />
+	0x20: (name=slow_lea) Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.
+ <br />
+	0x40: (name=single_mul) Number of Multiply packed/scalar single precision uops allocated
  <br />
 </td>
 
 </tr>
 
 <tr><td>arith</td><td>	Arithmetic </td><td> all</td><td>
-	0x01: fpu_div_active Cycles when divider is busy executing divide operations
- <br />
-	0x04: fpu_div Divide operations executed (extra: edge cmask=1)
+	0x01: (name=fpu_div_active) Cycles when divider is busy executing divide operations
+ <br />
+	0x04: (name=fpu_div) Divide operations executed
  <br />
 </td>
 
 </tr>
 
 <tr><td>l2_rqsts</td><td>	L2 cache requests </td><td> all</td><td>
-	0x01: demand_data_rd_hit Demand Data Read requests that hit L2 cache
- <br />
-	0x03: all_demand_data_rd Demand Data Read requests
- <br />
-	0x04: rfo_hit RFO requests that hit L2 cache
- <br />
-	0x08: rfo_miss RFO requests that miss L2 cache
- <br />
-	0x0c: all_rfo RFO requests to L2 cache
- <br />
-	0x10: code_rd_hit L2 cache hits when fetching instructions, code reads.
- <br />
-	0x20: code_rd_miss L2 cache misses when fetching instructions
- <br />
-	0x30: all_code_rd L2 code requests
- <br />
-	0x40: pf_hit Requests from the L2 hardware prefetchers that hit L2 cache
- <br />
-	0x80: pf_miss Requests from the L2 hardware prefetchers that miss L2 cache
- <br />
-	0xc0: all_pf Requests from L2 hardware prefetchers
+	0x01: (name=demand_data_rd_hit) Demand Data Read requests that hit L2 cache
+ <br />
+	0x03: (name=all_demand_data_rd) Demand Data Read requests
+ <br />
+	0x04: (name=rfo_hit) RFO requests that hit L2 cache
+ <br />
+	0x08: (name=rfo_miss) RFO requests that miss L2 cache
+ <br />
+	0x0c: (name=all_rfo) RFO requests to L2 cache
+ <br />
+	0x10: (name=code_rd_hit) L2 cache hits when fetching instructions, code reads.
+ <br />
+	0x20: (name=code_rd_miss) L2 cache misses when fetching instructions
+ <br />
+	0x30: (name=all_code_rd) L2 code requests
+ <br />
+	0x40: (name=pf_hit) Requests from the L2 hardware prefetchers that hit L2 cache
+ <br />
+	0x80: (name=pf_miss) Requests from the L2 hardware prefetchers that miss L2 cache
+ <br />
+	0xc0: (name=all_pf) Requests from L2 hardware prefetchers
  <br />
 </td>
 
 </tr>
 
 <tr><td>l2_store_lock_rqsts</td><td>	L2 cache store lock requests </td><td> all</td><td>
-	0x01: miss RFOs that miss cache lines
- <br />
-	0x08: hit_m RFOs that hit cache lines in M state
- <br />
-	0x0f: all RFOs that access cache lines in any state
+	0x01: (name=miss) RFOs that miss cache lines
+ <br />
+	0x08: (name=hit_m) RFOs that hit cache lines in M state
+ <br />
+	0x0f: (name=all) RFOs that access cache lines in any state
  <br />
 </td>
 
 </tr>
 
 <tr><td>l2_l1d_wb_rqsts</td><td>	writebacks from L1D to the L2 cache </td><td> all</td><td>
-	0x01: miss Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)
- <br />
-	0x04: hit_e Not rejected writebacks from L1D to L2 cache lines in E state
- <br />
-	0x08: hit_m Not rejected writebacks from L1D to L2 cache lines in M state
- <br />
-	0x0f: all Not rejected writebacks from L1D to L2 cache lines in any state.
+	0x01: (name=miss) Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)
+ <br />
+	0x04: (name=hit_e) Not rejected writebacks from L1D to L2 cache lines in E state
+ <br />
+	0x08: (name=hit_m) Not rejected writebacks from L1D to L2 cache lines in M state
+ <br />
+	0x0f: (name=all) Not rejected writebacks from L1D to L2 cache lines in any state.
  <br />
 </td>
 
 </tr>
 
 <tr><td>l1d_pend_miss</td><td>	L1D miss oustandings </td><td> 2</td><td>
-	0x01: pending L1D miss oustandings duration in cycles
- <br />
-	0x01: pending_cycles Cycles with L1D load Misses outstanding. (extra: cmask=1)
- <br />
-	0x01: occurences This event counts the number of L1D misses outstanding, using an edge detect to count transitions. (extra: edge cmask=1)
+	0x01: (name=pending) L1D miss oustandings duration in cycles
+ <br />
+	0x01: (name=pending_cycles) Cycles with L1D load Misses outstanding.
+ <br />
+	0x01: (name=occurences) This event counts the number of L1D misses outstanding, using an edge detect to count transitions.
  <br />
 </td>
 
 </tr>
 
 <tr><td>dtlb_store_misses</td><td>	Store misses in all DTLB levels that cause page walks </td><td> all</td><td>
-	0x01: miss_causes_a_walk Store misses in all DTLB levels that cause page walks
- <br />
-	0x02: walk_completed Store misses in all DTLB levels that cause completed page walks
- <br />
-	0x04: walk_duration Cycles when PMH is busy with page walks
- <br />
-	0x10: stlb_hit Store operations that miss the first TLB level but hit the second and do not cause page walks
+	0x01: (name=miss_causes_a_walk) Store misses in all DTLB levels that cause page walks
+ <br />
+	0x02: (name=walk_completed) Store misses in all DTLB levels that cause completed page walks
+ <br />
+	0x04: (name=walk_duration) Cycles when PMH is busy with page walks
+ <br />
+	0x10: (name=stlb_hit) Store operations that miss the first TLB level but hit the second and do not cause page walks
  <br />
 </td>
 
 </tr>
 
 <tr><td>load_hit_pre</td><td>	Load dispatches that hit fill buffer </td><td> all</td><td>
-	0x01: sw_pf Not software-prefetch load dispatches that hit forward buffer allocated for software prefetch
- <br />
-	0x02: hw_pf Not software-prefetch load dispatches that hit forward buffer allocated for hardware prefetch
+	0x01: (name=sw_pf) Not software-prefetch load dispatches that hit forward buffer allocated for software prefetch
+ <br />
+	0x02: (name=hw_pf) Not software-prefetch load dispatches that hit forward buffer allocated for hardware prefetch
  <br />
 </td>
 
 </tr>
 
 <tr><td>l1d</td><td>	L1D data line replacements </td><td> all</td><td>
-	0x01: replacement L1D data line replacements
+	0x01: (name=replacement) L1D data line replacements
  <br />
 </td>
 
 </tr>
 
 <tr><td>move_elimination</td><td>	Integer move elimination </td><td> all</td><td>
-	0x01: int_not_eliminated Number of integer Move Elimination candidate uops that were not eliminated.
- <br />
-	0x02: simd_not_eliminated Number of SIMD Move Elimination candidate uops that were not eliminated.
- <br />
-	0x04: int_eliminated Number of integer Move Elimination candidate uops that were eliminated.
- <br />
-	0x08: simd_eliminated Number of SIMD Move Elimination candidate uops that were eliminated.
+	0x01: (name=int_not_eliminated) Number of integer Move Elimination candidate uops that were not eliminated.
+ <br />
+	0x02: (name=simd_not_eliminated) Number of SIMD Move Elimination candidate uops that were not eliminated.
+ <br />
+	0x04: (name=int_eliminated) Number of integer Move Elimination candidate uops that were eliminated.
+ <br />
+	0x08: (name=simd_eliminated) Number of SIMD Move Elimination candidate uops that were eliminated.
  <br />
 </td>
 
 </tr>
 
 <tr><td>cpl_cycles</td><td>	Unhalted core cycles qualified by ring </td><td> all</td><td>
-	0x01: ring0 Unhalted core cycles when the thread is in ring 0
- <br />
-	0x01: ring0_trans Number of intervals between processor halts while thread is in ring 0 (extra: edge cmask=1)
- <br />
-	0x02: ring123 Unhalted core cycles when thread is in rings 1, 2, or 3
+	0x01: (name=ring0) Unhalted core cycles when the thread is in ring 0
+ <br />
+	0x01: (name=ring0_trans) Number of intervals between processor halts while thread is in ring 0
+ <br />
+	0x02: (name=ring123) Unhalted core cycles when thread is in rings 1, 2, or 3
  <br />
 </td>
 
 </tr>
 
 <tr><td>rs_events</td><td>	Reservation station </td><td> all</td><td>
-	0x01: empty_cycles Cycles when Reservation Station (RS) is empty for the thread
+	0x01: (name=empty_cycles) Cycles when Reservation Station (RS) is empty for the thread
  <br />
 </td>
 
 </tr>
 
 <tr><td>tlb_access</td><td>	TLB access </td><td> all</td><td>
-	0x04: load_stlb_hit Load operations that miss the first DTLB level but hit the second and do not cause page walks
+	0x04: (name=load_stlb_hit) Load operations that miss the first DTLB level but hit the second and do not cause page walks
  <br />
 </td>
 
 </tr>
 
 <tr><td>offcore_requests_outstanding</td><td>	Offcore outstanding transactions </td><td> all</td><td>
-	0x01: demand_data_rd Offcore outstanding Demand Data Read transactions in uncore queue.
- <br />
-	0x01: cycles_with_demand_data_rd Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore (extra: cmask=1)
- <br />
-	0x02: demand_code_rd Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle
- <br />
-	0x04: demand_rfo Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore
- <br />
-	0x04: cycles_with_demand_rfo Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle (extra: cmask=1)
- <br />
-	0x08: all_data_rd Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore
- <br />
-	0x08: cycles_with_data_rd Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore (extra: cmask=1)
+	0x01: (name=demand_data_rd) Offcore outstanding Demand Data Read transactions in uncore queue.
+ <br />
+	0x01: (name=cycles_with_demand_data_rd) Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore
+ <br />
+	0x02: (name=demand_code_rd) Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle
+ <br />
+	0x04: (name=demand_rfo) Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore
+ <br />
+	0x04: (name=cycles_with_demand_rfo) Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle
+ <br />
+	0x08: (name=all_data_rd) Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore
+ <br />
+	0x08: (name=cycles_with_data_rd) Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore
  <br />
 </td>
 
 </tr>
 
 <tr><td>lock_cycles</td><td>	Locked cycles </td><td> all</td><td>
-	0x01: split_lock_uc_lock_duration Cycles when L1 and L2 are locked due to UC or split lock
- <br />
-	0x02: cache_lock_duration Cycles when L1D is locked
- <br />
-</td>
-
-</tr>
-
-<tr><td>idq</td><td>	Instruction Decode Queue (IDQ) </td><td> 0, 1, 2, 3</td><td>
-	0x02: empty Instruction Decode Queue (IDQ) empty cycles
- <br />
-	0x04: mite_uops Uops delivered to Instruction Decode Queue (IDQ) from MITE path
- <br />
-	0x04: mite_cycles Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path (extra: cmask=1)
- <br />
-	0x08: dsb_uops Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
- <br />
-	0x08: dsb_cycles Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path (extra: cmask=1)
- <br />
-	0x10: ms_dsb_uops Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
- <br />
-	0x10: ms_dsb_cycles Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy (extra: cmask=1)
- <br />
-	0x10: ms_dsb_occur Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy (extra: edge cmask=1)
- <br />
-	0x18: all_dsb_cycles_any_uops Cycles Decode Stream Buffer (DSB) is delivering any Uop (extra: cmask=1)
- <br />
-	0x18: all_dsb_cycles_4_uops Cycles Decode Stream Buffer (DSB) is delivering 4 Uops (extra: cmask=4)
- <br />
-	0x20: ms_mite_uops Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
- <br />
-	0x24: all_mite_cycles_any_uops Cycles MITE is delivering any Uop (extra: cmask=1)
- <br />
-	0x24: all_mite_cycles_4_uops Cycles MITE is delivering 4 Uops (extra: cmask=4)
- <br />
-	0x30: ms_uops Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
- <br />
-	0x30: ms_cycles Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy (extra: cmask=1)
- <br />
-	0x3c: mite_all_uops Uops delivered to Instruction Decode Queue (IDQ) from MITE path
+	0x01: (name=split_lock_uc_lock_duration) Cycles when L1 and L2 are locked due to UC or split lock
+ <br />
+	0x02: (name=cache_lock_duration) Cycles when L1D is locked
+ <br />
+</td>
+
+</tr>
+
+<tr><td>idq</td><td>	Instruction Decode Queue (IDQ) </td><td> all</td><td>
+	0x02: (name=empty) Instruction Decode Queue (IDQ) empty cycles
+ <br />
+	0x04: (name=mite_uops) Uops delivered to Instruction Decode Queue (IDQ) from MITE path
+ <br />
+	0x04: (name=mite_cycles) Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path
+ <br />
+	0x08: (name=dsb_uops) Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path
+ <br />
+	0x08: (name=dsb_cycles) Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path
+ <br />
+	0x10: (name=ms_dsb_uops) Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
+ <br />
+	0x10: (name=ms_dsb_cycles) Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
+ <br />
+	0x10: (name=ms_dsb_occur) Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy
+ <br />
+	0x18: (name=all_dsb_cycles_any_uops) Cycles Decode Stream Buffer (DSB) is delivering any Uop
+ <br />
+	0x18: (name=all_dsb_cycles_4_uops) Cycles Decode Stream Buffer (DSB) is delivering 4 Uops
+ <br />
+	0x20: (name=ms_mite_uops) Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
+ <br />
+	0x24: (name=all_mite_cycles_any_uops) Cycles MITE is delivering any Uop
+ <br />
+	0x24: (name=all_mite_cycles_4_uops) Cycles MITE is delivering 4 Uops
+ <br />
+	0x30: (name=ms_uops) Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
+ <br />
+	0x30: (name=ms_cycles) Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy
+ <br />
+	0x3c: (name=mite_all_uops) Uops delivered to Instruction Decode Queue (IDQ) from MITE path
  <br />
 </td>
 
 </tr>
 
 <tr><td>icache</td><td>	Instruction cache </td><td> all</td><td>
-	0x02: misses Instruction cache, streaming buffer and victim cache misses
+	0x02: (name=misses) Instruction cache, streaming buffer and victim cache misses
  <br />
 </td>
 
 </tr>
 
 <tr><td>itlb_misses</td><td>	Misses at all ITLB levels that cause page walks </td><td> all</td><td>
-	0x01: miss_causes_a_walk Misses at all ITLB levels that cause page walks
- <br />
-	0x02: walk_completed Misses in all ITLB levels that cause completed page walks
- <br />
-	0x04: walk_duration Cycles when PMH is busy with page walks
- <br />
-	0x10: stlb_hit Operations that miss the first ITLB level but hit the second and do not cause any page walks
+	0x01: (name=miss_causes_a_walk) Misses at all ITLB levels that cause page walks
+ <br />
+	0x02: (name=walk_completed) Misses in all ITLB levels that cause completed page walks
+ <br />
+	0x04: (name=walk_duration) Cycles when PMH is busy with page walks
+ <br />
+	0x10: (name=stlb_hit) Operations that miss the first ITLB level but hit the second and do not cause any page walks
  <br />
 </td>
 
 </tr>
 
 <tr><td>ild_stall</td><td>	Stalls caused by changing prefix length of the instruction. </td><td> all</td><td>
-	0x01: lcp Stalls caused by changing prefix length of the instruction.
- <br />
-	0x04: iq_full Stall cycles because IQ is full
+	0x01: (name=lcp) Stalls caused by changing prefix length of the instruction.
+ <br />
+	0x04: (name=iq_full) Stall cycles because IQ is full
  <br />
 </td>
 
 </tr>
 
 <tr><td>br_inst_exec</td><td>	Branch instructions </td><td> all</td><td>
-	0x41: nontaken_conditional Not taken macro-conditional branches
- <br />
-	0x81: taken_conditional Taken speculative and retired macro-conditional branches
- <br />
-	0x82: taken_direct_jump Taken speculative and retired macro-conditional branch instructions excluding calls and indirects
- <br />
-	0x84: taken_indirect_jump_non_call_ret Taken speculative and retired indirect branches excluding calls and returns
- <br />
-	0x88: taken_indirect_near_return Taken speculative and retired indirect branches with return mnemonic
- <br />
-	0x90: taken_direct_near_call Taken speculative and retired direct near calls
- <br />
-	0xa0: taken_indirect_near_call Taken speculative and retired indirect calls
- <br />
-	0xc1: all_conditional Speculative and retired macro-conditional branches
- <br />
-	0xc2: all_direct_jmp Speculative and retired macro-unconditional branches excluding calls and indirects
- <br />
-	0xc4: all_indirect_jump_non_call_ret Speculative and retired indirect branches excluding calls and returns
- <br />
-	0xc8: all_indirect_near_return Speculative and retired indirect return branches.
- <br />
-	0xd0: all_direct_near_call Speculative and retired direct near calls
- <br />
-	0xff: all_branches Speculative and retired branches
+	0x41: (name=nontaken_conditional) Not taken macro-conditional branches
+ <br />
+	0x81: (name=taken_conditional) Taken speculative and retired macro-conditional branches
+ <br />
+	0x82: (name=taken_direct_jump) Taken speculative and retired macro-conditional branch instructions excluding calls and indirects
+ <br />
+	0x84: (name=taken_indirect_jump_non_call_ret) Taken speculative and retired indirect branches excluding calls and returns
+ <br />
+	0x88: (name=taken_indirect_near_return) Taken speculative and retired indirect branches with return mnemonic
+ <br />
+	0x90: (name=taken_direct_near_call) Taken speculative and retired direct near calls
+ <br />
+	0xa0: (name=taken_indirect_near_call) Taken speculative and retired indirect calls
+ <br />
+	0xc1: (name=all_conditional) Speculative and retired macro-conditional branches
+ <br />
+	0xc2: (name=all_direct_jmp) Speculative and retired macro-unconditional branches excluding calls and indirects
+ <br />
+	0xc4: (name=all_indirect_jump_non_call_ret) Speculative and retired indirect branches excluding calls and returns
+ <br />
+	0xc8: (name=all_indirect_near_return) Speculative and retired indirect return branches.
+ <br />
+	0xd0: (name=all_direct_near_call) Speculative and retired direct near calls
+ <br />
+	0xff: (name=all_branches) Speculative and retired branches
  <br />
 </td>
 
 </tr>
 
 <tr><td>br_misp_exec</td><td>	Mispredicted branch instructions </td><td> all</td><td>
-	0x41: nontaken_conditional Not taken speculative and retired mispredicted macro conditional branches
- <br />
-	0x81: taken_conditional Taken speculative and retired mispredicted macro conditional branches
- <br />
-	0x84: taken_indirect_jump_non_call_ret Taken speculative and retired mispredicted indirect branches excluding calls and returns
- <br />
-	0x88: taken_return_near Taken speculative and retired mispredicted indirect branches with return mnemonic
- <br />
-	0xa0: taken_indirect_near_call Taken speculative and retired mispredicted indirect calls
- <br />
-	0xc1: all_conditional Speculative and retired mispredicted macro conditional branches
- <br />
-	0xc4: all_indirect_jump_non_call_ret Mispredicted indirect branches excluding calls and returns
- <br />
-	0xff: all_branches Speculative and retired mispredicted macro conditional branches
+	0x41: (name=nontaken_conditional) Not taken speculative and retired mispredicted macro conditional branches
+ <br />
+	0x81: (name=taken_conditional) Taken speculative and retired mispredicted macro conditional branches
+ <br />
+	0x84: (name=taken_indirect_jump_non_call_ret) Taken speculative and retired mispredicted indirect branches excluding calls and returns
+ <br />
+	0x88: (name=taken_return_near) Taken speculative and retired mispredicted indirect branches with return mnemonic
+ <br />
+	0xa0: (name=taken_indirect_near_call) Taken speculative and retired mispredicted indirect calls
+ <br />
+	0xc1: (name=all_conditional) Speculative and retired mispredicted macro conditional branches
+ <br />
+	0xc4: (name=all_indirect_jump_non_call_ret) Mispredicted indirect branches excluding calls and returns
+ <br />
+	0xff: (name=all_branches) Speculative and retired mispredicted macro conditional branches
  <br />
 </td>
 
 </tr>
 
 <tr><td>idq_uops_not_delivered</td><td>	Uops not delivered by the Frontend to the Backend of the machine, while there is no Backend stall </td><td> all</td><td>
-	0x01: core Uops not delivered by the Frontend to the Backend of the machine, while there is no Backend stall
- <br />
-	0x01: cycles_le_3_uop_deliv.core Cycles with 3 or less uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall (extra: cmask=1)
- <br />
-	0x01: cycles_fe_was_ok Cycles with 4 uops delivered by the Frontend to the Backend of the machine, or the Backend was stalling (extra: inv cmask=1)
- <br />
-	0x01: cycles_le_2_uop_deliv.core Cycles with 2 or less uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall (extra: cmask=2)
- <br />
-	0x01: cycles_le_1_uop_deliv.core Cycles with 1 or less uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall (extra: cmask=3)
- <br />
-	0x01: cycles_0_uops_deliv.core Cycles with no uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall (extra: cmask=4)
+	0x01: (name=core) Uops not delivered by the Frontend to the Backend of the machine, while there is no Backend stall
+ <br />
+	0x01: (name=cycles_le_3_uop_deliv.core) Cycles with 3 or less uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall
+ <br />
+	0x01: (name=cycles_fe_was_ok) Cycles with 4 uops delivered by the Frontend to the Backend of the machine, or the Backend was stalling
+ <br />
+	0x01: (name=cycles_le_2_uop_deliv.core) Cycles with 2 or less uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall
+ <br />
+	0x01: (name=cycles_le_1_uop_deliv.core) Cycles with 1 or less uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall
+ <br />
+	0x01: (name=cycles_0_uops_deliv.core) Cycles with no uops delivered by the Frontend to the Backend of the machine, while there is no Backend stall
  <br />
 </td>
 
 </tr>
 
 <tr><td>uops_dispatched_port</td><td>	Cycles per thread when uops are dispatched to port </td><td> all</td><td>
-	0x01: port_0 Cycles per thread when uops are dispatched to port 0
- <br />
-	0x01: port_0_core Cycles per core when uops are dispatched to port 0 (extra:)
- <br />
-	0x02: port_1 Cycles per thread when uops are dispatched to port 1
- <br />
-	0x02: port_1_core Cycles per core when uops are dispatched to port 1 (extra:)
- <br />
-	0x0c: port_2 Cycles per thread when load or STA uops are dispatched to port 2
- <br />
-	0x0c: port_2_core Cycles per core when load or STA uops are dispatched to port 2 (extra:)
- <br />
-	0x30: port_3 Cycles per thread when load or STA uops are dispatched to port 3
- <br />
-	0x30: port_3_core Cycles per core when load or STA uops are dispatched to port 3 (extra:)
- <br />
-	0x40: port_4 Cycles per thread when uops are dispatched to port 4
- <br />
-	0x40: port_4_core Cycles per core when uops are dispatched to port 4 (extra:)
- <br />
-	0x80: port_5 Cycles per thread when uops are dispatched to port 5
- <br />
-	0x80: port_5_core Cycles per core when uops are dispatched to port 5 (extra:)
+	0x01: (name=port_0) Cycles per thread when uops are dispatched to port 0
+ <br />
+	0x01: (name=port_0_core) Cycles per core when uops are dispatched to port 0
+ <br />
+	0x02: (name=port_1) Cycles per thread when uops are dispatched to port 1
+ <br />
+	0x02: (name=port_1_core) Cycles per core when uops are dispatched to port 1
+ <br />
+	0x0c: (name=port_2) Cycles per thread when load or STA uops are dispatched to port 2
+ <br />
+	0x0c: (name=port_2_core) Cycles per core when load or STA uops are dispatched to port 2
+ <br />
+	0x30: (name=port_3) Cycles per thread when load or STA uops are dispatched to port 3
+ <br />
+	0x30: (name=port_3_core) Cycles per core when load or STA uops are dispatched to port 3
+ <br />
+	0x40: (name=port_4) Cycles per thread when uops are dispatched to port 4
+ <br />
+	0x40: (name=port_4_core) Cycles per core when uops are dispatched to port 4
+ <br />
+	0x80: (name=port_5) Cycles per thread when uops are dispatched to port 5
+ <br />
+	0x80: (name=port_5_core) Cycles per core when uops are dispatched to port 5
  <br />
 </td>
 
 </tr>
 
 <tr><td>resource_stalls</td><td>	Resource-related stall cycles </td><td> all</td><td>
-	0x01: any Resource-related stall cycles
- <br />
-	0x04: rs Cycles stalled due to no eligible RS entry available.
- <br />
-	0x08: sb Cycles stalled due to no store buffers available. (not including draining form sync).
- <br />
-	0x10: rob Cycles stalled due to re-order buffer full.
+	0x01: (name=any) Resource-related stall cycles
+ <br />
+	0x04: (name=rs) Cycles stalled due to no eligible RS entry available.
+ <br />
+	0x08: (name=sb) Cycles stalled due to no store buffers available. (not including draining form sync).
+ <br />
+	0x10: (name=rob) Cycles stalled due to re-order buffer full.
  <br />
 </td>
 
 </tr>
 
 <tr><td>cycle_activity</td><td>	Cycle activity </td><td> 2</td><td>
-	0x01: cycles_l2_pending Cycles with pending L2 cache miss loads. (extra: cmask=1)
- <br />
-	0x02: cycles_ldm_pending Cycles with pending memory loads. (extra: cmask=2)
- <br />
-	0x04: cycles_no_execute Total execution stalls (extra: cmask=4)
- <br />
-	0x05: stalls_l2_pending Execution stalls due to L2 cache misses. (extra: cmask=5)
- <br />
-	0x06: stalls_ldm_pending Execution stalls due to memory subsystem. (extra: cmask=6)
- <br />
-	0x08: cycles_l1d_pending Cycles with pending L1 cache miss loads. (extra: cmask=8)
- <br />
-	0x0c: stalls_l1d_pending Execution stalls due to L1 data cache misses (extra: cmask=c)
+	0x01: (name=cycles_l2_pending) Cycles with pending L2 cache miss loads.
+ <br />
+	0x02: (name=cycles_ldm_pending) Cycles with pending memory loads.
+ <br />
+	0x04: (name=cycles_no_execute) Total execution stalls
+ <br />
+	0x05: (name=stalls_l2_pending) Execution stalls due to L2 cache misses.
+ <br />
+	0x06: (name=stalls_ldm_pending) Execution stalls due to memory subsystem.
+ <br />
+	0x08: (name=cycles_l1d_pending) Cycles with pending L1 cache miss loads.
+ <br />
+	0x0c: (name=stalls_l1d_pending) Execution stalls due to L1 data cache misses
  <br />
 </td>
 
 </tr>
 
 <tr><td>dsb2mite_switches</td><td>	Decode Stream Buffer (DSB)-to-MITE switches </td><td> all</td><td>
-	0x01: count Decode Stream Buffer (DSB)-to-MITE switches
+	0x01: (name=count) Decode Stream Buffer (DSB)-to-MITE switches
  <br />
 </td>
 
 </tr>
 
 <tr><td>dsb_fill</td><td>	Decode Stream Buffer (DSB) fill </td><td> all</td><td>
-	0x08: exceed_dsb_lines Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines
+	0x08: (name=exceed_dsb_lines) Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines
  <br />
 </td>
 
 </tr>
 
 <tr><td>itlb</td><td>	Instruction TLB (ITLB) </td><td> all</td><td>
-	0x01: itlb_flush Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
+	0x01: (name=itlb_flush) Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.
  <br />
 </td>
 
 </tr>
 
 <tr><td>offcore_requests</td><td>	Uncore requests </td><td> all</td><td>
-	0x01: demand_data_rd Demand Data Read requests sent to uncore
- <br />
-	0x02: demand_code_rd Cacheable and noncachaeble code read requests
- <br />
-	0x04: demand_rfo Demand RFO requests including regular RFOs, locks, ItoM
- <br />
-	0x08: all_data_rd Demand and prefetch data reads
- <br />
-</td>
-
-</tr>
-
-<tr><td>uops_executed</td><td>	Uops executed </td><td> 0, 1, 2, 3</td><td>
-	0x01: thread Counts the number of uops to be executed per-thread each cycle.
- <br />
-	0x01: cycles_ge_1_uop_exec Cycles where at least 1 uop was executed per-thread (extra: cmask=1)
- <br />
-	0x01: stall_cycles Counts number of cycles no uops were dispatched to be executed on this thread. (extra: inv cmask=1)
- <br />
-	0x01: cycles_ge_2_uops_exec Cycles where at least 2 uops were executed per-thread (extra: cmask=2)
- <br />
-	0x01: cycles_ge_3_uops_exec Cycles where at least 3 uops were executed per-thread (extra: cmask=3)
- <br />
-	0x01: cycles_ge_4_uops_exec Cycles where at least 4 uops were executed per-thread (extra: cmask=4)
- <br />
-	0x02: core Number of uops executed on the core.
+	0x01: (name=demand_data_rd) Demand Data Read requests sent to uncore
+ <br />
+	0x02: (name=demand_code_rd) Cacheable and noncachaeble code read requests
+ <br />
+	0x04: (name=demand_rfo) Demand RFO requests including regular RFOs, locks, ItoM
+ <br />
+	0x08: (name=all_data_rd) Demand and prefetch data reads
+ <br />
+</td>
+
+</tr>
+
+<tr><td>uops_executed</td><td>	Uops executed </td><td> all</td><td>
+	0x01: (name=thread) Counts the number of uops to be executed per-thread each cycle.
+ <br />
+	0x01: (name=cycles_ge_1_uop_exec) Cycles where at least 1 uop was executed per-thread
+ <br />
+	0x01: (name=stall_cycles) Counts number of cycles no uops were dispatched to be executed on this thread.
+ <br />
+	0x01: (name=cycles_ge_2_uops_exec) Cycles where at least 2 uops were executed per-thread
+ <br />
+	0x01: (name=cycles_ge_3_uops_exec) Cycles where at least 3 uops were executed per-thread
+ <br />
+	0x01: (name=cycles_ge_4_uops_exec) Cycles where at least 4 uops were executed per-thread
+ <br />
+	0x02: (name=core) Number of uops executed on the core.
  <br />
 </td>
 
 </tr>
 
 <tr><td>tlb_flush</td><td>	DTLB flushes </td><td> all</td><td>
-	0x01: dtlb_thread DTLB flush attempts of the thread-specific entries
- <br />
-	0x20: stlb_any STLB flush attempts
+	0x01: (name=dtlb_thread) DTLB flush attempts of the thread-specific entries
+ <br />
+	0x20: (name=stlb_any) STLB flush attempts
  <br />
 </td>
 
 </tr>
 
 <tr><td>other_assists</td><td>	Microcode assists. </td><td> all</td><td>
-	0x08: avx_store Number of AVX memory assist for stores. AVX microcode assist is being invoked whenever the hardware is unable to properly handle AVX-256b operations.
- <br />
-	0x10: avx_to_sse Number of transitions from AVX-256 to legacy SSE when penalty applicable.
- <br />
-	0x20: sse_to_avx Number of transitions from SSE to AVX-256 when penalty applicable.
- <br />
-</td>
-
-</tr>
-
-<tr><td>uops_retired</td><td>	Retired uops. </td><td> 0, 1, 2, 3</td><td>
-	0x01: all Actually retired uops.
- <br />
-	0x01: stall_cycles Cycles without actually retired uops. (extra: inv cmask=1)
- <br />
-	0x01: core_stall_cycles Cycles without actually retired uops. (extra: inv cmask=1)
- <br />
-	0x01: total_cycles Cycles with less than 10 actually retired uops. (extra: inv cmask=10)
- <br />
-	0x02: retire_slots Retirement slots used.
+	0x08: (name=avx_store) Number of AVX memory assist for stores. AVX microcode assist is being invoked whenever the hardware is unable to properly handle AVX-256b operations.
+ <br />
+	0x10: (name=avx_to_sse) Number of transitions from AVX-256 to legacy SSE when penalty applicable.
+ <br />
+	0x20: (name=sse_to_avx) Number of transitions from SSE to AVX-256 when penalty applicable.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>uops_retired</td><td>	Retired uops. </td><td> all</td><td>
+	0x01: (name=all) Actually retired uops.
+ <br />
+	0x01: (name=stall_cycles) Cycles without actually retired uops.
+ <br />
+	0x01: (name=core_stall_cycles) Cycles without actually retired uops.
+ <br />
+	0x01: (name=total_cycles) Cycles with less than 10 actually retired uops.
+ <br />
+	0x02: (name=retire_slots) Retirement slots used.
  <br />
 </td>
 
 </tr>
 
 <tr><td>machine_clears</td><td>	Machine clears </td><td> all</td><td>
-	0x02: memory_ordering Counts the number of machine clears due to memory order conflicts.
- <br />
-	0x04: smc Self-modifying code (SMC) detected.
- <br />
-	0x20: maskmov This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
+	0x02: (name=memory_ordering) Counts the number of machine clears due to memory order conflicts.
+ <br />
+	0x04: (name=smc) Self-modifying code (SMC) detected.
+ <br />
+	0x20: (name=maskmov) This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.
  <br />
 </td>
 
 </tr>
 
 <tr><td>br_inst_retired</td><td>	Conditional branch instructions retired. </td><td> all</td><td>
-	0x01: conditional Conditional branch instructions retired.
- <br />
-	0x02: near_call_r3 Direct and indirect macro near call instructions retired (captured in ring 3).
- <br />
-	0x02: near_call Direct and indirect near call instructions retired.
- <br />
-	0x08: near_return Return instructions retired.
- <br />
-	0x10: not_taken Not taken branch instructions retired.
- <br />
-	0x20: near_taken Taken branch instructions retired.
- <br />
-	0x40: far_branch Far branch instructions retired.
+	0x01: (name=conditional) Conditional branch instructions retired.
+ <br />
+	0x02: (name=near_call_r3) Direct and indirect macro near call instructions retired (captured in ring 3).
+ <br />
+	0x02: (name=near_call) Direct and indirect near call instructions retired.
+ <br />
+	0x08: (name=near_return) Return instructions retired.
+ <br />
+	0x10: (name=not_taken) Not taken branch instructions retired.
+ <br />
+	0x20: (name=near_taken) Taken branch instructions retired.
+ <br />
+	0x40: (name=far_branch) Far branch instructions retired.
  <br />
 </td>
 
 </tr>
 
 <tr><td>br_misp_retired</td><td>	Mispredicted conditional branch instructions retired. </td><td> all</td><td>
-	0x01: conditional Mispredicted conditional branch instructions retired.
- <br />
-	0x20: near_taken number of near branch instructions retired that were mispredicted and taken.
- <br />
-</td>
-
-</tr>
-
-<tr><td>fp_assist</td><td>	FPU assists </td><td> 0, 1, 2, 3</td><td>
-	0x02: x87_output Number of X87 assists due to output value.
- <br />
-	0x04: x87_input Number of X87 assists due to input value.
- <br />
-	0x08: simd_output Number of SIMD FP assists due to Output values
- <br />
-	0x10: simd_input Number of SIMD FP assists due to input values
- <br />
-	0x1e: any Cycles with any input/output SSE or FP assist (extra: cmask=1)
+	0x01: (name=conditional) Mispredicted conditional branch instructions retired.
+ <br />
+	0x20: (name=near_taken) number of near branch instructions retired that were mispredicted and taken.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>fp_assist</td><td>	FPU assists </td><td> all</td><td>
+	0x02: (name=x87_output) Number of X87 assists due to output value.
+ <br />
+	0x04: (name=x87_input) Number of X87 assists due to input value.
+ <br />
+	0x08: (name=simd_output) Number of SIMD FP assists due to Output values
+ <br />
+	0x10: (name=simd_input) Number of SIMD FP assists due to input values
+ <br />
+	0x1e: (name=any) Cycles with any input/output SSE or FP assist
  <br />
 </td>
 
 </tr>
 
 <tr><td>rob_misc_events</td><td>	ROB (Register Order Buffer) events </td><td> all</td><td>
-	0x20: lbr_inserts Count cases of saving new LBR
- <br />
-</td>
-
-</tr>
-
-<tr><td>mem_uops_retired</td><td>	Memory Uops </td><td> 0, 1, 2, 3</td><td>
-	0x11: stlb_miss_loads Load uops with true STLB miss retired to architected path.
- <br />
-	0x12: stlb_miss_stores Store uops with true STLB miss retired to architected path.
- <br />
-	0x21: lock_loads Load uops with locked access retired to architected path.
- <br />
-	0x41: split_loads Line-splitted load uops retired to architected path.
- <br />
-	0x42: split_stores Line-splitted store uops retired to architected path.
- <br />
-	0x81: all_loads Load uops retired to architected path with filter on bits 0 and 1 applied.
- <br />
-	0x82: all_stores Store uops retired to architected path with filter on bits 0 and 1 applied.
- <br />
-</td>
-
-</tr>
-
-<tr><td>mem_load_uops_retired</td><td>	Memory load uops </td><td> 0, 1, 2, 3</td><td>
-	0x01: l1_hit Retired load uops with L1 cache hits as data sources.
- <br />
-	0x02: l2_hit Retired load uops with L2 cache hits as data sources.
- <br />
-	0x04: llc_hit Retired load uops which data sources were data hits in LLC without snoops required.
- <br />
-	0x40: hit_lfb Retired load uops which data sources were load uops missed L1 but hit forward buffer due to preceding miss to the same cache line with data not ready.
- <br />
-</td>
-
-</tr>
-
-<tr><td>mem_load_uops_llc_hit_retired</td><td>	Memory load uops with LLC (Last Level Cache) hit </td><td> 0, 1, 2, 3</td><td>
-	0x01: xsnp_miss Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
- <br />
-	0x02: xsnp_hit Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.
- <br />
-	0x04: xsnp_hitm Retired load uops which data sources were HitM responses from shared LLC.
- <br />
-	0x08: xsnp_none Retired load uops which data sources were hits in LLC without snoops required.
- <br />
-</td>
-
-</tr>
-
-<tr><td>mem_load_uops_llc_miss_retired</td><td>	Memory load uops with LLC (Last Level Cache) miss </td><td> 0, 1, 2, 3</td><td>
-	0x01: local_dram Data from local DRAM either Snoop not needed or Snoop Miss (RspI)
+	0x20: (name=lbr_inserts) Count cases of saving new LBR
+ <br />
+</td>
+
+</tr>
+
+<tr><td>mem_uops_retired</td><td>	Memory Uops </td><td> all</td><td>
+	0x11: (name=stlb_miss_loads) Load uops with true STLB miss retired to architected path.
+ <br />
+	0x12: (name=stlb_miss_stores) Store uops with true STLB miss retired to architected path.
+ <br />
+	0x21: (name=lock_loads) Load uops with locked access retired to architected path.
+ <br />
+	0x41: (name=split_loads) Line-splitted load uops retired to architected path.
+ <br />
+	0x42: (name=split_stores) Line-splitted store uops retired to architected path.
+ <br />
+	0x81: (name=all_loads) Load uops retired to architected path with filter on bits 0 and 1 applied.
+ <br />
+	0x82: (name=all_stores) Store uops retired to architected path with filter on bits 0 and 1 applied.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>mem_load_uops_retired</td><td>	Memory load uops </td><td> all</td><td>
+	0x01: (name=l1_hit) Retired load uops with L1 cache hits as data sources.
+ <br />
+	0x02: (name=l2_hit) Retired load uops with L2 cache hits as data sources.
+ <br />
+	0x04: (name=llc_hit) Retired load uops which data sources were data hits in LLC without snoops required.
+ <br />
+	0x40: (name=hit_lfb) Retired load uops which data sources were load uops missed L1 but hit forward buffer due to preceding miss to the same cache line with data not ready.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>mem_load_uops_llc_hit_retired</td><td>	Memory load uops with LLC (Last Level Cache) hit </td><td> all</td><td>
+	0x01: (name=xsnp_miss) Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.
+ <br />
+	0x02: (name=xsnp_hit) Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.
+ <br />
+	0x04: (name=xsnp_hitm) Retired load uops which data sources were HitM responses from shared LLC.
+ <br />
+	0x08: (name=xsnp_none) Retired load uops which data sources were hits in LLC without snoops required.
+ <br />
+</td>
+
+</tr>
+
+<tr><td>mem_load_uops_llc_miss_retired</td><td>	Memory load uops with LLC (Last Level Cache) miss </td><td> all</td><td>
+	0x01: (name=local_dram) Data from local DRAM either Snoop not needed or Snoop Miss (RspI)
  <br />
 </td>
 
 </tr>
 
 <tr><td>baclears</td><td>	Frontend resteering </td><td> all</td><td>
-	0x1f: any Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
+	0x1f: (name=any) Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.
  <br />
 </td>
 
 </tr>
 
 <tr><td>l2_trans</td><td>	L2 cache transactions </td><td> all</td><td>
-	0x01: demand_data_rd Demand Data Read requests that access L2 cache
- <br />
-	0x02: rfo RFO requests that access L2 cache
- <br />
-	0x04: code_rd L2 cache accesses when fetching instructions
- <br />
-	0x08: all_pf L2 or LLC HW prefetches that access L2 cache
- <br />
-	0x10: l1d_wb L1D writebacks that access L2 cache
- <br />
-	0x20: l2_fill L2 fill requests that access L2 cache
- <br />
-	0x40: l2_wb L2 writebacks that access L2 cache
- <br />
-	0x80: all_requests Transactions accessing L2 pipe
+	0x01: (name=demand_data_rd) Demand Data Read requests that access L2 cache
+ <br />
+	0x02: (name=rfo) RFO requests that access L2 cache
+ <br />
+	0x04: (name=code_rd) L2 cache accesses when fetching instructions
+ <br />
+	0x08: (name=all_pf) L2 or LLC HW prefetches that access L2 cache
+ <br />
+	0x10: (name=l1d_wb) L1D writebacks that access L2 cache
+ <br />
+	0x20: (name=l2_fill) L2 fill requests that access L2 cache
+ <br />
+	0x40: (name=l2_wb) L2 writebacks that access L2 cache
+ <br />
+	0x80: (name=all_requests) Transactions accessing L2 pipe
  <br />
 </td>
 
 </tr>
 
 <tr><td>l2_lines_in</td><td>	L2 cache lines in </td><td> all</td><td>
-	0x01: i L2 cache lines in I state filling L2
- <br />
-	0x02: s L2 cache lines in S state filling L2
- <br />
-	0x04: e L2 cache lines in E state filling L2
- <br />
-	0x07: all L2 cache lines filling L2
+	0x01: (name=i) L2 cache lines in I state filling L2
+ <br />
+	0x02: (name=s) L2 cache lines in S state filling L2
+ <br />
+	0x04: (name=e) L2 cache lines in E state filling L2
+ <br />
+	0x07: (name=all) L2 cache lines filling L2
  <br />
 </td>
 
 </tr>
 
 <tr><td>l2_lines_out</td><td>	L2 cache lines out </td><td> all</td><td>
-	0x01: demand_clean Clean L2 cache lines evicted by demand
- <br />
-	0x02: demand_dirty Dirty L2 cache lines evicted by demand
- <br />
-	0x04: pf_clean Clean L2 cache lines evicted by L2 prefetch
- <br />
-	0x08: pf_dirty Dirty L2 cache lines evicted by L2 prefetch
- <br />
-	0x0a: dirty_all Dirty L2 cache lines filling the L2
- <br />
-</td>
-
-</tr>
-
+	0x01: (name=demand_clean) Clean L2 cache lines evicted by demand
+ <br />
+	0x02: (name=demand_dirty) Dirty L2 cache lines evicted by demand
+ <br />
+	0x04: (name=pf_clean) Clean L2 cache lines evicted by L2 prefetch
+ <br />
+	0x08: (name=pf_dirty) Dirty L2 cache lines evicted by L2 prefetch
+ <br />
+	0x0a: (name=dirty_all) Dirty L2 cache lines filling the L2
+ <br />
+</td>
+
+</tr>
+