--- a/docs/ppc64-power8-events
+++ b/docs/ppc64-power8-events
@@ -83,7 +83,7 @@
 
 </tr>
 
-<tr><td>PM_INST_FROM_L3MISS</td><td>	A Instruction cacheline request resolved from a location that was beyond the local L3 cache </td><td> 2</td><td>
+<tr><td>PM_INST_FROM_L3MISS</td><td>         </td><td> 2</td><td>
 </td>
 
 </tr>
@@ -158,7 +158,7 @@
 
 </tr>
 
-<tr><td>PM_MRK_INST_FROM_L3MISS</td><td>	sampled instruction missed icache and came from beyond L3 A Instruction cacheline request for a marked/sampled instruction resolved from a location that was beyond the local L3 cache </td><td> 3</td><td>
+<tr><td>PM_MRK_INST_FROM_L3MISS</td><td>        cache </td><td> 3</td><td>
 </td>
 
 </tr>
@@ -218,42 +218,42 @@
 
 </tr>
 
-<tr><td>PM_THRESH_EXC_1024</td><td>	Threshold counter exceeded a value of 1024 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 1024 </td><td> 2</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_THRESH_EXC_128</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 128 </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_THRESH_EXC_2048</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 2048 </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_THRESH_EXC_256</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 256 </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_THRESH_EXC_32</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 32 </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_THRESH_EXC_4096</td><td>	Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 4096 </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_THRESH_EXC_512</td><td>	Threshold counter exceeded a value of 512 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 512 </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_THRESH_EXC_64</td><td>	Threshold counter exceeded a value of 64 Architecture provides a thresholding counter in MMCRA, it has a start and stop events to configure and a programmable threshold, this event increments when the threshold exceeded a count of 64 </td><td> 2</td><td>
+<tr><td>PM_THRESH_EXC_1024</td><td>        increments when the threshold exceeded a count of 1024 </td><td> 2</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_THRESH_EXC_128</td><td>        count of 128 </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_THRESH_EXC_2048</td><td>        count of 2048 </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_THRESH_EXC_256</td><td>        count of 256 </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_THRESH_EXC_32</td><td>        count of 32 </td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_THRESH_EXC_4096</td><td>        count of 4096 </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_THRESH_EXC_512</td><td>        increments when the threshold exceeded a count of 512 </td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_THRESH_EXC_64</td><td>        increments when the threshold exceeded a count of 64 </td><td> 2</td><td>
 </td>
 
 </tr>
@@ -303,7 +303,7 @@
 
 </tr>
 
-<tr><td>PM_CMPLU_STALL_DMISS_L21_L31</td><td>	Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). </td><td> 1</td><td>
+<tr><td>PM_CMPLU_STALL_DMISS_L21_L31</td><td>	Completion stall by Dcache miss. </td><td> 1</td><td>
 </td>
 
 </tr>
@@ -313,7 +313,7 @@
 
 </tr>
 
-<tr><td>PM_CMPLU_STALL_DMISS_L2L3_CONFLICT</td><td>	Completion stall due to cache miss resolving in core's L2/L3 with a conflict. </td><td> 3</td><td>
+<tr><td>PM_CMPLU_STALL_DMISS_L2L3_CONFLICT</td><td></td><td> 3</td><td>
 </td>
 
 </tr>
@@ -328,7 +328,7 @@
 
 </tr>
 
-<tr><td>PM_CMPLU_STALL_DMISS_REMOTE</td><td>	Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). </td><td> 1</td><td>
+<tr><td>PM_CMPLU_STALL_DMISS_REMOTE</td><td>	Completion stall due to cache miss resolving in core's Local Memory. </td><td> 1</td><td>
 </td>
 
 </tr>
@@ -443,42 +443,42 @@
 
 </tr>
 
-<tr><td>PM_DATA_FROM_L2</td><td>	The processor's data cache was reloaded from local core's L2 due to a demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_DATA_FROM_L2_NO_CONFLICT</td><td>	The processor's data cache was reloaded from local core's L2 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_DATA_FROM_L3</td><td>	The processor's data cache was reloaded from local core's L3 due to a demand load. </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_DATA_FROM_L3MISS_MOD</td><td>	The processor's data cache was reloaded from a localtion other than the local core's L3 due to a demand load. </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_DATA_FROM_L3_NO_CONFLICT</td><td>	The processor's data cache was reloaded from local core's L3 without conflict due to a demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_DATA_FROM_LMEM</td><td>	The processor's data cache was reloaded from the local chip's Memory due to a demand load. </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_DATA_FROM_MEMORY</td><td>	The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load. </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_DC_PREF_STREAM_STRIDED_CONF</td><td>	A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.. </td><td> 2</td><td>
+<tr><td>PM_DATA_FROM_L2</td><td>        load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_DATA_FROM_L2_NO_CONFLICT</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_DATA_FROM_L3</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_DATA_FROM_L3MISS_MOD</td><td>        to a demand load. </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_DATA_FROM_L3_NO_CONFLICT</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_DATA_FROM_LMEM</td><td>        </td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_DATA_FROM_MEMORY</td><td>        remote or distant due to a demand load. </td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_DC_PREF_STREAM_STRIDED_CONF</td><td></td><td> 2</td><td>
 </td>
 
 </tr>
@@ -493,17 +493,17 @@
 
 </tr>
 
-<tr><td>PM_GCT_NOSLOT_DISP_HELD_ISSQ</td><td>	Gct empty fo this thread due to dispatch hold on this thread due to Issue q full. </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_GCT_NOSLOT_DISP_HELD_OTHER</td><td>	Gct empty fo this thread due to dispatch hold on this thread due to sync. </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_GCT_NOSLOT_DISP_HELD_SRQ</td><td>	Gct empty fo this thread due to dispatch hold on this thread due to SRQ full. </td><td> 1</td><td>
+<tr><td>PM_GCT_NOSLOT_DISP_HELD_ISSQ</td><td>	Gct empty fo this thread due to Icache Miss and branch mispred. </td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_GCT_NOSLOT_DISP_HELD_OTHER</td><td></td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_GCT_NOSLOT_DISP_HELD_SRQ</td><td></td><td> 1</td><td>
 </td>
 
 </tr>
@@ -552,12 +552,12 @@
 
 </tr>
 
-<tr><td>PM_MRK_DATA_FROM_L2</td><td>	The processor's data cache was reloaded from local core's L2 due to a marked load. </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_L2MISS_CYC</td><td>	Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load. </td><td> 3</td><td>
+<tr><td>PM_MRK_DATA_FROM_L2</td><td>	Cycles L3 miss was pending for this thread. </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_L2MISS_CYC</td><td>        marked load. </td><td> 3</td><td>
 </td>
 
 </tr>
@@ -567,22 +567,22 @@
 
 </tr>
 
-<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT</td><td>	The processor's data cache was reloaded from local core's L2 without conflict due to a marked load. </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC</td><td>	Duration in cycles to reload from local core's L2 without conflict due to a marked load. </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_L3</td><td>	The processor's data cache was reloaded from local core's L3 due to a marked load. </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_L3MISS_CYC</td><td>	Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load. </td><td> 1</td><td>
+<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT</td><td>        marked load. </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC</td><td>        </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_L3</td><td>        </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_L3MISS_CYC</td><td>        marked load. </td><td> 1</td><td>
 </td>
 
 </tr>
@@ -592,42 +592,42 @@
 
 </tr>
 
-<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT</td><td>	The processor's data cache was reloaded from local core's L3 without conflict due to a marked load. </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC</td><td>	Duration in cycles to reload from local core's L3 without conflict due to a marked load. </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_LL4</td><td>	The processor's data cache was reloaded from the local chip's L4 cache due to a marked load. </td><td> 0</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_LL4_CYC</td><td>	Duration in cycles to reload from the local chip's L4 cache due to a marked load. </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_LMEM</td><td>	The processor's data cache was reloaded from the local chip's Memory due to a marked load. </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_LMEM_CYC</td><td>	Duration in cycles to reload from the local chip's Memory due to a marked load. </td><td> 3</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_MEMORY</td><td>	The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load. </td><td> 1</td><td>
-</td>
-
-</tr>
-
-<tr><td>PM_MRK_DATA_FROM_MEMORY_CYC</td><td>	Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load. </td><td> 3</td><td>
+<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT</td><td>        marked load. </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC</td><td>        </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_LL4</td><td>        load. </td><td> 0</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_LL4_CYC</td><td>        load. </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_LMEM</td><td>        </td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_LMEM_CYC</td><td>        </td><td> 3</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_MEMORY</td><td>        remote or distant due to a marked load. </td><td> 1</td><td>
+</td>
+
+</tr>
+
+<tr><td>PM_MRK_DATA_FROM_MEMORY_CYC</td><td>        distant due to a marked load. </td><td> 3</td><td>
 </td>
 
 </tr>