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<tr><td>CYCLES</td><td>	Cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_1PLUS_PPC_CMPL</td><td>	one or more ppc instructions finished </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_1PLUS_PPC_DISP</td><td>	Cycles at least one Instr Dispatched </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_ANY_THRD_RUN_CYC</td><td>	One of threads in run_cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_BR_MPRED_CMPL</td><td>	Number of Branch Mispredicts </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_BR_TAKEN_CMPL</td><td>	New event for Branch Taken </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CYC</td><td>	Cycles </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L2MISS</td><td>	Demand LD - L2 Miss (not L2 hit) </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS</td><td>	Demand LD - L3 Miss (not L2 hit and not L3 hit) </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_MEM</td><td>	data from Memory </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_DTLB_MISS</td><td>	Data PTEG reload </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_EXT_INT</td><td>	external interrupt </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_FLOP</td><td>	Floating Point Operations Finished </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_FLUSH</td><td>	Flush (any type) </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_CYC</td><td>	No itags assigned </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_IERAT_MISS</td><td>	Cycles Instruction ERAT was reloaded </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_INST_DISP</td><td>	Number of PPC Dispatched </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_INST_FROM_L3MISS</td><td>         </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_ITLB_MISS</td><td>	ITLB Reloaded (always zero on POWER6) </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_L1_DCACHE_RELOAD_VALID</td><td>	DL1 reloaded due to Demand Load </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_L1_ICACHE_MISS</td><td>	Demand iCache Miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_LD_MISS_L1</td><td>	Load Missed L1 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_LSU_DERAT_MISS</td><td>	DERAT Reloaded due to a DERAT miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_BR_MPRED_CMPL</td><td>	Marked Branch Mispredicted </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_MRK_BR_TAKEN_CMPL</td><td>	Marked Branch Taken completed </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS</td><td>	sampled load resolved beyond L2 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3MISS</td><td>	sampled load resolved beyond L3 </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_MEM</td><td>	sampled load resolved from memory </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DERAT_MISS</td><td>	Erat Miss (TLB Access) All page sizes </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_MRK_DTLB_MISS</td><td>	sampled Instruction dtlb miss </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_INST_CMPL</td><td>	Marked group complete </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_INST_DISP</td><td>	The thread has dispatched a randomly sampled marked instruction </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_INST_FROM_L3MISS</td><td>        cache </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_L1_ICACHE_MISS</td><td>	sampled Instruction suffered an icache Miss </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_L1_RELOAD_VALID</td><td>	Sampled Instruction had a data reload </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_LD_MISS_L1</td><td>	Marked DL1 Demand Miss </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_ST_CMPL</td><td>	marked store completed and sent to nest </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_RUN_CYC</td><td>	Run_cycles </td><td> 5</td><td>
</td>

</tr>

<tr><td>PM_RUN_INST_CMPL</td><td>	Run_Instructions </td><td> 4</td><td>
</td>

</tr>

<tr><td>PM_RUN_PURR</td><td>	Run_PURR </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_ST_FIN</td><td>	Store Instructions Finished </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_ST_MISS_L1</td><td>	Store Missed L1 </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_TB_BIT_TRANS</td><td>	timebase event </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRD_CONC_RUN_INST</td><td>	PPC Instructions Finished when both threads in run_cycles </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_1024</td><td>        increments when the threshold exceeded a count of 1024 </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_128</td><td>        count of 128 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_2048</td><td>        count of 2048 </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_256</td><td>        count of 256 </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_32</td><td>        count of 32 </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_4096</td><td>        count of 4096 </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_512</td><td>        increments when the threshold exceeded a count of 512 </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_THRESH_EXC_64</td><td>        increments when the threshold exceeded a count of 64 </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_THRESH_MET</td><td>	Threshold exceeded </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_BR_2PATH</td><td>	two path branch. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_BR_CMPL</td><td>	Branch Instruction completed. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_BR_MRK_2PATH</td><td>	marked two path branch. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL</td><td>	Completion stall. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_BRU</td><td>	Completion stall due to a Branch Unit. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_BRU_CRU</td><td>	Completion stall due to IFU. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_COQ_FULL</td><td>	Completion stall due to CO q full. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_DCACHE_MISS</td><td>	Completion stall by Dcache miss. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_DMISS_L21_L31</td><td>	Completion stall by Dcache miss. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_DMISS_L2L3</td><td>	Completion stall by Dcache miss which resolved in L2/L3. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_DMISS_L2L3_CONFLICT</td><td></td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_DMISS_L3MISS</td><td>	Completion stall due to cache miss resolving missed the L3. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_DMISS_LMEM</td><td>	Completion stall due to cache miss resolving in core's Local Memory. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_DMISS_REMOTE</td><td>	Completion stall due to cache miss resolving in core's Local Memory. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_ERAT_MISS</td><td>	Completion stall due to LSU reject ERAT miss. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_FLUSH</td><td>	completion stall due to flush by own thread. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_FXLONG</td><td>	Completion stall due to a long latency fixed point instruction. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_FXU</td><td>	Completion stall due to FXU. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_HWSYNC</td><td>	completion stall due to hwsync. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_LOAD_FINISH</td><td>	Completion stall due to a Load finish. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_LSU</td><td>	Completion stall by LSU instruction. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_LWSYNC</td><td>	completion stall due to isync/lwsync. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_MEM_ECC_DELAY</td><td>	Completion stall due to mem ECC delay. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_NTCG_FLUSH</td><td>	Completion stall due to reject (load hit store). </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_OTHER_CMPL</td><td>	Instructions core completed while this thread was stalled. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_REJECT</td><td>	Completion stall due to LSU reject. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_REJECT_LHS</td><td>	Completion stall due to reject (load hit store). </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_REJ_LMQ_FULL</td><td>	Completion stall due to LSU reject LMQ full. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_SCALAR</td><td>	Completion stall due to VSU scalar instruction. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_SCALAR_LONG</td><td>	Completion stall due to VSU scalar long latency instruction. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_STORE</td><td>	Completion stall by stores. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_ST_FWD</td><td>	Completion stall due to store forward. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_THRD</td><td>	Completion stall due to thread conflict. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_VECTOR</td><td>	Completion stall due to VSU vector instruction. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_VECTOR_LONG</td><td>	Completion stall due to VSU vector long instruction. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_CMPLU_STALL_VSU</td><td>	Completion stall due to VSU instruction. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L2</td><td>        load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L2_NO_CONFLICT</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L3</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20] . </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L3MISS_MOD</td><td>        to a demand load. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_L3_NO_CONFLICT</td><td>        demand load or demand load plus prefetch controlled by MMCR1[20]. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_LMEM</td><td>        </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_DATA_FROM_MEMORY</td><td>        remote or distant due to a demand load. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_DC_PREF_STREAM_STRIDED_CONF</td><td></td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_BR_MPRED</td><td>	Gct empty fo this thread due to branch mispred. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_BR_MPRED_ICMISS</td><td>	Gct empty fo this thread due to Icache Miss and branch mispred. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_DISP_HELD_ISSQ</td><td>	Gct empty fo this thread due to Icache Miss and branch mispred. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_DISP_HELD_OTHER</td><td></td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_DISP_HELD_SRQ</td><td></td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_IC_L3MISS</td><td>	Gct empty fo this thread due to icach l3 miss. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_GCT_NOSLOT_IC_MISS</td><td>	Gct empty fo this thread due to Icache Miss. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_GRP_DISP</td><td>. </td><td> 2</td><td>	dispatch_success Group Dispatched</td>

</tr>

<tr><td>PM_GRP_MRK</td><td>	Instruction marked in idu. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_HV_CYC</td><td>	cycles in hypervisor mode . </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_INST_CMPL</td><td>	PPC Instructions Finished (completed). </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_IOPS_CMPL</td><td>	IOPS Completed. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_LD_CMPL</td><td>	count of Loads completed. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_LD_L3MISS_PEND_CYC</td><td>	Cycles L3 miss was pending for this thread. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2</td><td>	Cycles L3 miss was pending for this thread. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2MISS_CYC</td><td>        marked load. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_CYC</td><td>	Duration in cycles to reload from local core's L2 due to a marked load. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT</td><td>        marked load. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC</td><td>        </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3</td><td>        </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3MISS_CYC</td><td>        marked load. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_CYC</td><td>	Duration in cycles to reload from local core's L3 due to a marked load. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT</td><td>        marked load. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC</td><td>        </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LL4</td><td>        load. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LL4_CYC</td><td>        load. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LMEM</td><td>        </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_LMEM_CYC</td><td>        </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_MEMORY</td><td>        remote or distant due to a marked load. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_DATA_FROM_MEMORY_CYC</td><td>        distant due to a marked load. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_GRP_CMPL</td><td>	marked instruction finished (completed). </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_INST_DECODED</td><td>	marked instruction decoded. Name from ISU? </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_L2_RC_DISP</td><td>	Marked Instruction RC dispatched in L2. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_MRK_LD_MISS_L1_CYC</td><td>	Marked ld latency. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_MRK_STALL_CMPLU_CYC</td><td>	Marked Group Completion Stall cycles (use edge detect to count ). </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_NEST_REF_CLK</td><td>	Nest reference clocks. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_PMC1_OVERFLOW</td><td>	Overflow from counter 1. </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_PMC2_OVERFLOW</td><td>	Overflow from counter 2. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_PMC3_OVERFLOW</td><td>	Overflow from counter 3. </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_PMC4_OVERFLOW</td><td>	Overflow from counter 4. </td><td> 0</td><td>
</td>

</tr>

<tr><td>PM_PMC6_OVERFLOW</td><td>	Overflow from counter 6. </td><td> 2</td><td>
</td>

</tr>

<tr><td>PM_PPC_CMPL</td><td>	PPC Instructions Finished (completed). </td><td> 3</td><td>
</td>

</tr>

<tr><td>PM_THRD_ALL_RUN_CYC</td><td>	All Threads in Run_cycles (was both threads in run_cycles). </td><td> 1</td><td>
</td>

</tr>

<tr><td>PM_THRESH_NOT_MET</td><td>	Threshold counter did not meet threshold. </td><td> 3</td><td>
</td>

</tr>