From: Ray B. <ra...@mp...> - 2006-07-24 22:27:55
|
Bring oprofile events and unit_mask definitions for Opteron up to date with the 3.85 (October 2005) version of the "BIOS and Kernel Developer's Guide for the AMD Athlon[tm] 64 and AMD Opteron[tm] Processors," AMD Publication # 26094. Also, increase the number of unit masks to correctly support event 0xE9. Signed-off-by: Ray Bryant <ra...@mp...> Index: oprofile-0.9.1/libop/op_events.h =================================================================== --- oprofile-0.9.1.orig/libop/op_events.h +++ oprofile-0.9.1/libop/op_events.h @@ -28,8 +28,8 @@ enum unit_mask_type { utm_bitmask /**< bitmask */ }; -/** up to sixteen allowed unit masks */ -#define MAX_UNIT_MASK 16 +/** up to thirty-two allowed unit masks */ +#define MAX_UNIT_MASK 32 /** Describe an unit mask. */ Index: oprofile-0.9.1/events/x86-64/hammer/events =================================================================== --- oprofile-0.9.1.orig/events/x86-64/hammer/events +++ oprofile-0.9.1/events/x86-64/hammer/events @@ -1,81 +1,122 @@ +# ################################################################################### +# Copyright (c) 2006 Advanced Micro Devices, Inc. +# Contributed by Ray Bryant <ra...@mp...> +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +# of the Software, and to permit persons to whom the Software is furnished to do so, +# subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +# INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +# PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF +# CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +# OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################### +# # Hammer events # +# Updated to match 3.85 (October 2005) version of the +# "BIOS and Kernel Developer's Guide for the AMD Athlon[tm] 64 and +# AMD Opteron[tm] Processors," AMD Publication # 26094. +# Ray Bryant, ra...@mp..., 7/24/2006. +# +# As much as possible, event names have been changed to match the BKDG. +# event_select's have been changed to upper case hex for consistency +# event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state -event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSNS : Retired instructions (includes exceptions, interrupts, re-syncs) -event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_OPS : Retired ops -event:0x80 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_FETCHES : Instruction cache fetches -event:0x81 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses +event:0xC0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs) +event:0xC1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops +event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches (RevE) +event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses -event:0x42 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_L2 : Data cache refills from L2 +# Note: unit mask 0x01 counts same events as event select 0x43 +event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM : Data cache refills from L2 or system event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system -event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_WRITEBACKS : Data cache write backs -event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCHES : Retired branches (conditional, unconditional, exceptions, interrupts) -event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCHES_MISPREDICTED : Retired branches mispredicted -event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCHES : Retired taken branches -event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCHES_MISPREDICTED : Retired taken branches mispredicted -event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISSES_L2_DTLB_HITS : L1 DTLB misses and L2 DTLB hits -event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_DTLB_MISSES : L1 and L2 DTLB misses -event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_DATA_REFS : Misaligned data references -event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISSES_L2_ITLB_HITS : L1 ITLB misses (and L2 ITLB hits) -event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_ITLB_MISSES : L1 and L2 ITLB misses -event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers -event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_RESYNC_BRANCHES : Retired re-sync branches (only non-control transfer branches) -event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED : Interrupts masked cycles (IF=0) -event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_PENDING : Interrupts masked while pending cycles (INTR while IF=0) -event:0xcf counters:0,1,2,3 um:zero minimum:10 name:HARDWARE_INTERRUPTS : Number of taken hardware interrupts +event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted +event:0xC2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts) +event:0xC3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired Mispredicted Branch Instructions +event:0xC4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions +event:0xC5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted +event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits +event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses +event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses +event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB misses (and L2 ITLB hits) +event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB Miss, L2 ITLB Miss +event:0xC6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers +event:0xC7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches) +event:0xCD counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0) +event:0xCE counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending +event:0xCF counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops -event:0x01 counters:0,1,2,3 um:zero minimum:500 name:NO_FPU_OPS : Cycles with no FPU ops retired -event:0x02 counters:0,1,2,3 um:zero minimum:500 name:FAST_FPU_OPS : Dispatched FPU ops that use the fast flag interface -event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEG_REG_LOAD : Segment register load -event:0x21 counters:0,1,2,3 um:zero minimum:500 name:SELF_MODIFY_RESYNC : Micro-architectural re-sync caused by self modifying code -event:0x22 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_RESYNC : Micro-architectural re-sync caused by snoop -event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_FULL : LS Buffer 2 Full -event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOCKED_OP : Locked operation +event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired +event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface +event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads +event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code +event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop +event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 Full +event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOCKED_OPS : Locked operations +# not in the 3.28 BKDG, was in BKDG 3.24 event:0x25 counters:0,1,2,3 um:zero minimum:500 name:OP_LATE_CANCEL : Micro-architectural late cancel of an operation -event:0x26 counters:0,1,2,3 um:zero minimum:500 name:CFLUSH_RETIRED : Retired CFLUSH instructions -event:0x27 counters:0,1,2,3 um:zero minimum:500 name:CPUID_RETIRED : Retired CPUID instructions -event:0x48 counters:0,1,2,3 um:zero minimum:500 name:ACCESS_CANCEL_LATE : Micro-architectural late cancel of an access -event:0x49 counters:0,1,2,3 um:zero minimum:500 name:ACCESS_CANCEL_EARLY : Micro-architectural early cancel of an access -event:0x4A counters:0,1,2,3 um:ecc minimum:500 name:ECC_BIT_ERR : One bit ECC error recorded by scrubber -event:0x4B counters:0,1,2,3 um:prefetch minimum:500 name:DISPATCHED_PRE_INSTRS : Dispatched prefetch instructions -event:0x7D counters:0,1,2,3 um:l2_internal minimum:500 name:BU_INT_L2_REQ : Internal L2 request -event:0x7E counters:0,1,2,3 um:l2_req_miss minimum:500 name:BU_FILL_REQ : Fill request that missed in L2 -event:0x7F counters:0,1,2,3 um:l2_fill minimum:500 name:BU_FILL_L2 : Fill into L2 -event:0x82 counters:0,1,2,3 um:zero minimum:500 name:IC_REFILL_FROM_L2 : Refill from L2 -event:0x83 counters:0,1,2,3 um:zero minimum:500 name:IC_REFILL_FROM_SYS : Refill from system -event:0x86 counters:0,1,2,3 um:zero minimum:500 name:IC_RESYNC_BY_SNOOP : Micro-architectural re-sync caused by snoop -event:0x88 counters:0,1,2,3 um:zero minimum:500 name:IC_STACK_HIT : Return stack hit -event:0x87 counters:0,1,2,3 um:zero minimum:500 name:IC_FETCH_STALL : Instruction fetch stall -event:0x89 counters:0,1,2,3 um:zero minimum:500 name:IC_STACK_OVERFLOW : Return stack overflow +event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH instructions +event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID instructions +event:0x48 counters:0,1,2,3 um:zero minimum:500 name:MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS : Micro-architectural late cancel of an access +event:0x49 counters:0,1,2,3 um:zero minimum:500 name:MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS : Micro-architectural early cancel of an access +event:0x4A counters:0,1,2,3 um:ecc minimum:500 name:SCRUBBER_SINGLE_BIT_ECC_ERRORS : One bit ECC error recorded by scrubber +event:0x4B counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : Prefetch Instructions Dispatched +event:0x4C counters:0,1,2,3 um:zero minimum:500 name:DCACHE_MISS_LOCKED_INSTRUCTIONS : DCACHE Misses by Locked Instructions +event:0x65 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory Requests by Type +event:0x67 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data Prefetcher +event:0x6C counters:0,1,2,3 um:systemreadresponse minimum:500 name:SYSTEM_READ_RESPONSES : System Read Responses by Coherency State +event:0x6D counters:0,1,2,3 um:zero minimum:500 name:QUADWORD_WRITE_TRANSFERS : Quadwords Written to System +event:0x7D counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 Cache +event:0x7E counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 Cache Misses +event:0x7F counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 Fill/Writeback +event:0x82 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction Cache Refills from L2 +event:0x83 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction Cache Refills from System +event:0x86 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE : Pipeline Restart Due to Instruction Stream Probe +event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall +event:0x88 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return stack hit +event:0x89 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return stack overflow event:0xC8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired near returns -event:0xc9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_RETURNS_MISPREDICT : Retired near returns mispredicted -event:0xca counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_MISCOMPARE : Returned taken branches mispredicted due to address miscompare -event:0xcb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_FPU_INSTRS : Retired FPU instructions -event:0xcc counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_INSTRS : Retired FastPath double-op instructions -event:0xd0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty) -event:0xd1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls -event:0xd2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FROM_BRANCH_ABORT : Dispatch stall from branch abort to retire -event:0xd3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_SERIALIZATION : Dispatch stall for serialization -event:0xd4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_SEG_LOAD : Dispatch stall for segment load -event:0xd5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_REORDER_BUFFER : Dispatch stall when reorder buffer is full -event:0xd6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_RESERVE_STATIONS : Dispatch stall when reservation stations are full -event:0xd7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FPU : Dispatch stall when FPU is full -event:0xd8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_LS : Dispatch stall when LS is full -event:0xd9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_QUIET_WAIT : Dispatch stall when waiting for all to be quiet -event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_PENDING : Dispatch stall when far control transfer or re-sync branch is pending -event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:1 name:FPU_EXCEPTIONS : FPU exceptions -event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : Number of breakpoints for DR0 -event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : Number of breakpoints for DR1 -event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : Number of breakpoints for DR2 -event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : Number of breakpoints for DR3 -event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:MEM_PAGE_ACCESS : Memory controller page access -event:0xe1 counters:0,1,2,3 um:zero minimum:500 name:MEM_PAGE_TBL_OVERFLOW : Memory controller page table overflow -event:0xe2 counters:0,1,2,3 um:zero minimum:500 name:DRAM_SLOTS_MISSED : Memory controller DRAM command slots missed (in MemClks) -event:0xe3 counters:0,1,2,3 um:turnaround minimum:500 name:MEM_TURNAROUND : Memory controller turnaround -event:0xe4 counters:0,1,2,3 um:saturation minimum:500 name:MEM_BYPASS_SAT : Memory controller bypass saturation -event:0xeb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized Commands -event:0xec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESULT : Probe Result -event:0xf6 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_BUS0_WIDTH : HyperTransport(tm) bus 0 bandwidth -event:0xf7 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_BUS1_WIDTH : HyperTransport(tm) bus 1 bandwidth -event:0xf8 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_BUS2_WIDTH : HyperTransport(tm) bus 2 bandwidth +event:0xC9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns mispredicted +event:0xCA counters:0,1,2,3 um:zero minimum:500 name:RETIRED_INDIRECT_BRANCHES_MISPREDICTED : Retired Indirect Branches Mispredicted +event:0xCB counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX/FP_INSTRUCTIONS : Retired MMX/FP instructions +event:0xCC counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS : Retired FastPath double-op instructions +event:0xD0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty) +event:0xD1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls +event:0xD2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch stall from branch abort to retire +event:0xD3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SERIALIZATION : Dispatch stall for serialization +event:0xD4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SEGMENT_LOAD : Dispatch stall for segment load +event:0xD5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_REORDER_BUFFER_FULL : Dispatch stall for reorder buffer full +event:0xD6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_RESERVATION_STATION_FULL : Dispatch stall when reservation stations are full +event:0xD7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FPU_FULL : Dispatch stall when FPU is full +event:0xD8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch stall when LS is full +event:0xD9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch stall when waiting for all to be quiet +event:0xDA counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch Stall for Far Transfer or Resync to Retire +event:0xDB counters:0,1,2,3 um:fpu_exceptions minimum:1 name:FPU_EXCEPTIONS : FPU exceptions +event:0xDC counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : Number of breakpoints for DR0 +event:0xDD counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : Number of breakpoints for DR1 +event:0xDE counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : Number of breakpoints for DR2 +event:0xDF counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : Number of breakpoints for DR3 +event:0xE0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM Accesses +event:0xE1 counters:0,1,2,3 um:zero minimum:500 name:MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS : Memory controller page table overflows +event:0xE3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory controller turnarounds +event:0xE4 counters:0,1,2,3 um:saturation minimum:500 name:MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION : Memory controller bypass saturation +event:0xE8 counters:0,1,2,3 um:zero minimum:500 name:DRAM_ECC_ERRORS : ECC Errors +event:0xEE counters:0,1,2,3 um:gart minimum:500 name:GART_EVENTS : GART Events +event:0xE5 counters:0,1,2,3 um:sizedblocks minimum:500 name:SIZED_BLOCKS : Sized Blocks +event:0xE9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU/IO_REQUESTS_TO_MEMORY/IO : CPU/IO Requests to Memory/IO (RevE) +event:0xEA counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache Block Commands (RevE) +event:0xEB counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized Commands +event:0xEC counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe Responses and Upstream Requests +event:0xF6 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_LINK0_BANDWIDTH : HyperTransport(tm) link 0 bandwidth +event:0xF7 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_LINK1_BANDWIDTH : HyperTransport(tm) link 1 bandwidth +event:0xF8 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_LINK2_BANDWIDTH : HyperTransport(tm) link 2 bandwidth Index: oprofile-0.9.1/events/x86-64/hammer/unit_masks =================================================================== --- oprofile-0.9.1.orig/events/x86-64/hammer/unit_masks +++ oprofile-0.9.1/events/x86-64/hammer/unit_masks @@ -1,26 +1,56 @@ -# Athlon possible unit masks +# ################################################################################### +# Copyright (c) 2006 Advanced Micro Devices, Inc. +# Contributed by Ray Bryant <ra...@mp...> # -# See "Bios and Kernel Developer's Guide for the AMD Athlon 64 and AMD Opteron -# Processors" (publication #26094) +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies +# of the Software, and to permit persons to whom the Software is furnished to do so, +# subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +# INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +# PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF +# CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE +# OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# ################################################################################### +# +# Hammer unit masks +# +# Updated to match 3.85 (October 2005) version of the +# "BIOS and Kernel Developer's Guide for the AMD Athlon[tm] 64 and +# AMD Opteron[tm] Processors," AMD Publication # 26094. +# Ray Bryant, ra...@mp..., 7/24/2006 # - name:zero type:mandatory default:0x0 0x0 No unit mask -name:moesi type:bitmask default:0x1f +name:moesi type:bitmask default:0x1F 0x10 (M)odified cache state 0x08 (O)wner cache state 0x04 (E)xclusive cache state 0x02 (S)hared cache state 0x01 (I)nvalid cache state - 0x1f All cache states -name:fpu_ops type:bitmask default:0x3f - 0x01 Add pipe ops excluding junk ops - 0x02 Multiply pipe ops excluding junk ops - 0x04 Store pipe ops excluding junk ops - 0x08 Add pipe junk ops - 0x10 Multiple pipe junk ops - 0x20 Store pipe junk ops -name:segregload type:bitmask default:0x7f + 0x1F All cache states +name:moess type:bitmask default:0x1E + 0x10 (M)odified cache state + 0x08 (O)wner cache state + 0x04 (E)xclusive cache state + 0x02 (S)hared cache state + 0x01 refill from system + 0x1E All cache states except Invalid +name:fpu_ops type:bitmask default:0x3F + 0x01 Add pipe ops + 0x02 Multiply pipe + 0x04 Store pipe ops + 0x08 Add pipe load ops + 0x10 Multiply pipe load ops + 0x20 Store pipe load ops +name:segregload type:bitmask default:0x7F 0x01 ES register 0x02 CS register 0x04 SS register @@ -35,7 +65,7 @@ name:prefetch type:bitmask default:0x07 0x01 Load 0x02 Store 0x04 NTA -name:fpu_instr type:bitmask default:0x0f +name:fpu_instr type:bitmask default:0x0F 0x01 x87 instructions 0x02 Combined MMX & 3DNow instructions 0x04 Combined packed SSE & SSE2 instructions @@ -44,7 +74,7 @@ name:fpu_fastpath type:bitmask default:0 0x01 With low op in position 0 0x02 With low op in position 1 0x04 With low op in position 2 -name:fpu_exceptions type:bitmask default:0x0f +name:fpu_exceptions type:bitmask default:0x0F 0x01 x87 reclass microfaults 0x02 SSE retype microfaults 0x04 SSE reclass microfaults @@ -57,21 +87,20 @@ name:turnaround type:bitmask default:0x0 0x01 DIMM turnaround 0x02 Read to write turnaround 0x04 Write to read turnaround -name:saturation type:bitmask default:0x0f +name:saturation type:bitmask default:0x0F 0x01 Memory controller high priority bypass 0x02 Memory controller low priority bypass 0x04 DRAM controller interface bypass 0x08 DRAM controller queue bypass -name:sizecmds type:bitmask default:0x7f -# FIXME: can we get some non-gobbledegook ? - 0x01 NonPostWrSzByte - 0x02 NonPostWrSzDWord - 0x04 PostWrSzByte - 0x08 PostWrSzDWord - 0x10 RdSzByte - 0x20 RdSzDword - 0x40 RdModWr -name:probe type:bitmask default:0x0f +name:sizecmds type:bitmask default:0x7F + 0x01 non-posted write byte + 0x02 non-posted write dword + 0x04 posted write byte + 0x08 posted write dword + 0x10 read byte (4 bytes) + 0x20 read dword (1-16 dwords) + 0x40 read-modify-write +name:probe type:bitmask default:0x0F 0x01 Probe miss 0x02 Probe hit 0x04 Probe hit dirty without memory cancel @@ -81,7 +110,7 @@ name:ht type:bitmask default:0x7 0x02 Data sent 0x04 Buffer release sent 0x08 NOP sent -name:l2_internal type:bitmask default:0x1f +name:l2_internal type:bitmask default:0x1F 0x01 IC fill 0x02 DC fill 0x04 TLB reload @@ -94,3 +123,57 @@ name:l2_req_miss type:bitmask default:0x name:l2_fill type:bitmask default:0x03 0x01 Dirty L2 victim 0x02 Victim from L1 +name:gart type:bitmask default:0x07 + 0x01 GART aperture hit on access from CPU + 0x02 GART aperture hit on access from I/O + 0x04 GART miss +name:sizedblocks type:bitmask default:0x3C + 0x04 32-byte Sized Writes (RevD) + 0x08 64-byte Sized Writes (RevD) + 0x10 32-byte Sized Reads (RevD) + 0x20 64-byte Sized Reads (RevD) +name:cpiorequests type:bitmask default:0xA2 + 0xA2 Requests Local I/O to Local Memory + 0xA1 Requests Local I/O to Local I/O + 0xA3 Requests Local I/O to Local Any + 0xAA Requests Local Any to Local Memory + 0xA5 Requests Local Any to Local I/O + 0xAF Requests Local Any to Local Any + 0x98 Requests Local CPU to Remote Memory + 0x94 Requests Local CPU to Remote I/O + 0x9C Requests Local CPU to Remote Any + 0x92 Requests Local I/O to Remote Memory + 0x91 Requests Local I/O to Remote I/O + 0x93 Requests Local I/O to Remote Any + 0x9A Requests Local Any to Remote Memory + 0x95 Requests Local Any to Remote I/O + 0x9F Requests Local Any to Remote Any + 0xB8 Requests Local CPU to Any Memory + 0xB4 Requests Local CPU to Any I/O + 0xBC Requests Local CPU to Any Any + 0xB2 Requests Local I/O to Any Memory + 0xB1 Requests Local I/O to Any I/O + 0xB3 Requests Local I/O to Any Any + 0xBA Requests Local Any to Any Memory + 0xB5 Requests Local Any to Any I/O + 0xBF Requests Local Any to Any Any + 0x64 Requests Remote CPU to Local I/O + 0x61 Requests Remote I/O to Local I/O + 0x65 Requests Remote Any to Local I/O +name:cacheblock type:bitmask default:0x3D + 0x01 Victim Block (Writeback) + 0x04 Read Block (Dcache load miss refill) + 0x08 Read Block Shared (Icache refill) + 0x10 Read Block Modified (Dcache store miss refill) + 0x20 Change to Dirty (first store to clean block already in cache) +name:dataprefetch type:bitmask default:0x03 + 0x01 Cancelled prefetches + 0x02 Prefetch attempts +name:memreqtype type:bitmask default:0x83 + 0x01 Requests to non-cacheable (UC) memory + 0x02 Requests to write-combining (WC) memory or WC buffer flushes to WB memory + 0x80 Streaming store (SS) requests +name:systemreadresponse type:bitmask default:0x7 + 0x01 Exclusive + 0x02 Modified + 0x04 Shared -- Ray Bryant AMD Performance Labs Austin, Tx 512-602-0038 (o) 512-507-7807 (c) |
From: John L. <le...@mo...> - 2006-07-25 10:48:48
|
On Mon, Jul 24, 2006 at 05:27:27PM -0500, Ray Bryant wrote: > -/** up to sixteen allowed unit masks */ > -#define MAX_UNIT_MASK 16 > +/** up to thirty-two allowed unit masks */ > +#define MAX_UNIT_MASK 32 Have we got rid of all the places where unit mask was a u16? > +# ################################################################################### > +# Copyright (c) 2006 Advanced Micro Devices, Inc. > +# Contributed by Ray Bryant <ra...@mp...> > +# > +# Permission is hereby granted, free of charge, to any person obtaining a copy > +# of this software and associated documentation files (the "Software"), to deal > +# in the Software without restriction, including without limitation the rights > +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies > +# of the Software, and to permit persons to whom the Software is furnished to do so, > +# subject to the following conditions: > +# > +# The above copyright notice and this permission notice shall be included in all > +# copies or substantial portions of the Software. > +# > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, > +# INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A > +# PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > +# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF > +# CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE > +# OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > +# ################################################################################### Hmm... why the new license? You're modifying the GPL code and this appears to grant extra privileges. Your copyright notice is fine, but you can't change the license, and I don't think we need the changelog entry in the file. > -event:0xf8 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_BUS2_WIDTH : HyperTransport(tm) bus 2 bandwidth > +event:0xC9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns mispredicted And a real nit - why uppercase hex? We use lowercase everywhere else. cheers john |
From: Ray B. <ra...@mp...> - 2006-07-25 15:04:25
|
On Tuesday 25 July 2006 05:48, you wrote: > On Mon, Jul 24, 2006 at 05:27:27PM -0500, Ray Bryant wrote: > > -/** up to sixteen allowed unit masks */ > > -#define MAX_UNIT_MASK 16 > > +/** up to thirty-two allowed unit masks */ > > +#define MAX_UNIT_MASK 32 > > Have we got rid of all the places where unit mask was a u16? > Hi John, I'll look. > > +# > > ######################################################################### > >########## +# Copyright (c) 2006 Advanced Micro Devices, Inc. > > +# Contributed by Ray Bryant <ra...@mp...> > > +# > > +# Permission is hereby granted, free of charge, to any person obtaining > > a copy +# of this software and associated documentation files (the > > "Software"), to deal +# in the Software without restriction, including > > without limitation the rights +# to use, copy, modify, merge, publish, > > distribute, sublicense, and/or sell copies +# of the Software, and to > > permit persons to whom the Software is furnished to do so, +# subject to > > the following conditions: > > +# > > +# The above copyright notice and this permission notice shall be > > included in all +# copies or substantial portions of the Software. > > +# > > +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > > EXPRESS OR IMPLIED, +# INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > > MERCHANTABILITY, FITNESS FOR A +# PARTICULAR PURPOSE AND NONINFRINGEMENT. > > IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +# HOLDERS BE LIABLE FOR ANY > > CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF +# CONTRACT, > > TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE > > SOFTWARE +# OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > > +# > > ######################################################################### > >########## > > Hmm... why the new license? You're modifying the GPL code and this > appears to grant extra privileges. > This is what AMD legal wants to do. I will go back and ask again. > Your copyright notice is fine, but you can't change the license, and I > don't think we need the changelog entry in the file. > OK. > > -event:0xf8 counters:0,1,2,3 um:ht minimum:500 > > name:HYPERTRANSPORT_BUS2_WIDTH : HyperTransport(tm) bus 2 bandwidth > > +event:0xC9 counters:0,1,2,3 um:zero minimum:500 > > name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns > > mispredicted > > And a real nit - why uppercase hex? We use lowercase everywhere else. > Ah, for some reason it was mixed case in my file, and I didn't like the inconsistency, so I [tried, apparently] changing them all to upper case. All lower case works fine as well. I'll fix. > cheers > john > > ------------------------------------------------------------------------- > Take Surveys. Earn Cash. Influence the Future of IT > Join SourceForge.net's Techsay panel and you'll get the chance to share > your opinions on IT & business topics through brief surveys -- and earn > cash > http://www.techsay.com/default.php?page=join.php&p=sourceforge&CID=DEVDEV > _______________________________________________ > oprofile-list mailing list > opr...@li... > https://lists.sourceforge.net/lists/listinfo/oprofile-list -- Ray Bryant AMD Performance Labs Austin, Tx 512-602-0038 (o) 512-507-7807 (c) |
From: William C. <wc...@re...> - 2006-07-25 13:59:42
|
Ray Bryant wrote: > Bring oprofile events and unit_mask definitions for Opteron up to date > with the 3.85 (October 2005) version of the "BIOS and Kernel Developer's > Guide for the AMD Athlon[tm] 64 and AMD Opteron[tm] Processors," AMD > Publication # 26094. > > Also, increase the number of unit masks to correctly support event 0xE9. > > Signed-off-by: Ray Bryant <ra...@mp...> Hi Ray, The patch is against oprofile-0.9.1 and doesn't apply cleanly to the cvs version of OProfile. It doesn't seem to apply cleanly to 0.9.1 either. Maybe my mail reader munged something in the patch. The following is the result of applying the patch the the oprofile cvs: $ patch -p1 < ../Update\ for\ events\ and\ unit_masks\ for\ Opteron.eml patching file libop/op_events.h patching file events/x86-64/hammer/events Hunk #1 FAILED at 1. 1 out of 1 hunk FAILED -- saving rejects to file events/x86-64/hammer/events.rejpatching file events/x86-64/hammer/unit_masks Hunk #1 FAILED at 1. Hunk #2 succeeded at 66 (offset 1 line). Hunk #4 succeeded at 88 (offset 1 line). Hunk #6 FAILED at 123. 2 out of 6 hunks FAILED -- saving rejects to file events/x86-64/hammer/unit_masks.rej Shouldn't the license be GPL like the rest of OProfile? Having the software in the same tarball with different licenses seems a bit compicated. There are some pieces of software that have been dual licensed by the copyright owner, e.g. cygwin. However, those changes have applied over the entire package. -Will |
From: Ray B. <ra...@mp...> - 2006-07-25 15:09:59
|
On Tuesday 25 July 2006 08:59, you wrote: > Ray Bryant wrote: > > Bring oprofile events and unit_mask definitions for Opteron up to date > > with the 3.85 (October 2005) version of the "BIOS and Kernel Developer's > > Guide for the AMD Athlon[tm] 64 and AMD Opteron[tm] Processors," AMD > > Publication # 26094. > > > > Also, increase the number of unit masks to correctly support event 0xE9. > > > > Signed-off-by: Ray Bryant <ra...@mp...> > > Hi Ray, > > The patch is against oprofile-0.9.1 and doesn't apply cleanly to the cvs > version of OProfile. It doesn't seem to apply cleanly to 0.9.1 either. > Maybe my mail reader munged something in the patch. The following is the > result of applying the patch the the oprofile cvs: Hi Will, Grumble. I build a clean 0.9.1 tree and it doesn't apply cleanly for me either. I guess I've stepped on the original source code in my development tree somehow. Since I have to back to legal and discuss the license issue anyway, I'll have to send out a new patch. Sorry about that. > > $ patch -p1 < ../Update\ for\ events\ and\ unit_masks\ for\ Opteron.eml > patching file libop/op_events.h > patching file events/x86-64/hammer/events > Hunk #1 FAILED at 1. > 1 out of 1 hunk FAILED -- saving rejects to file > events/x86-64/hammer/events.rejpatching file > events/x86-64/hammer/unit_masks Hunk #1 FAILED at 1. > Hunk #2 succeeded at 66 (offset 1 line). > Hunk #4 succeeded at 88 (offset 1 line). > Hunk #6 FAILED at 123. > 2 out of 6 hunks FAILED -- saving rejects to file > events/x86-64/hammer/unit_masks.rej > > > > Shouldn't the license be GPL like the rest of OProfile? Having the > software in the same tarball with different licenses seems a bit > compicated. There are some pieces of software that have been dual > licensed by the copyright owner, e.g. cygwin. However, those changes > have applied over the entire package. > > -Will I'm just doing what AMD legal asked me to. I'll go back and ask again. > > > ------------------------------------------------------------------------- > Take Surveys. Earn Cash. Influence the Future of IT > Join SourceForge.net's Techsay panel and you'll get the chance to share > your opinions on IT & business topics through brief surveys -- and earn > cash > http://www.techsay.com/default.php?page=join.php&p=sourceforge&CID=DEVDEV > _______________________________________________ > oprofile-list mailing list > opr...@li... > https://lists.sourceforge.net/lists/listinfo/oprofile-list -- Ray Bryant AMD Performance Labs Austin, Tx 512-602-0038 (o) 512-507-7807 (c) |
From: William C. <wc...@re...> - 2006-07-26 14:46:59
|
Ray Bryant wrote: > On Tuesday 25 July 2006 08:59, you wrote: > >>Ray Bryant wrote: >> >>>Bring oprofile events and unit_mask definitions for Opteron up to date >>>with the 3.85 (October 2005) version of the "BIOS and Kernel Developer's >>>Guide for the AMD Athlon[tm] 64 and AMD Opteron[tm] Processors," AMD >>>Publication # 26094. >>> >>>Also, increase the number of unit masks to correctly support event 0xE9. >>> >>>Signed-off-by: Ray Bryant <ra...@mp...> >> >>Hi Ray, >> >>The patch is against oprofile-0.9.1 and doesn't apply cleanly to the cvs >>version of OProfile. It doesn't seem to apply cleanly to 0.9.1 either. >>Maybe my mail reader munged something in the patch. The following is the >>result of applying the patch the the oprofile cvs: > > > Hi Will, > > Grumble. I build a clean 0.9.1 tree and it doesn't apply cleanly for me > either. I guess I've stepped on the original source code in my development > tree somehow. > > Since I have to back to legal and discuss the license issue anyway, I'll have > to send out a new patch. Could you make sure the patch applies against the oprofile cvs repository? I don't think there have been changes recently on the amd64 event files, but using the cvs version will ensure that the patch applies. -Will |
From: Ray B. <ra...@mp...> - 2006-07-25 15:32:39
|
On Tuesday 25 July 2006 05:48, John Levon wrote: > > Hmm... why the new license? You're modifying the GPL code and this > appears to grant extra privileges. > I guess what happened here was I picked up a copy of the MIT license from the code I sent to perfmon. Would a BSD license be acceptable instead? I think legal is going to want some kind of license and disclaimer in the file itself for me to be able to send it out and it would help to have a proposal. If the only alternative is GPL, they tend to get nervous, but if that is what is required, so be it. > Your copyright notice is fine, but you can't change the license, and I > don't think we need the changelog entry in the file. > To my way of thinking, the user should be able to look at the file and find out what version of the BKDG the file was derived from. That way they can know whether or not the file has been updated to match a particular revision of processors. As new processors come out, we can keep the file updated with the corresponding BKDG version. So it seems to provide useful information, no? I don't care if it is a changelog entry or not, but I think the comment provides useful information. <snip> -- Ray Bryant AMD Performance Labs Austin, Tx 512-602-0038 (o) 512-507-7807 (c) |
From: John L. <le...@mo...> - 2006-07-25 16:04:09
|
On Tue, Jul 25, 2006 at 10:32:25AM -0500, Ray Bryant wrote: > > Hmm... why the new license? You're modifying the GPL code and this > > appears to grant extra privileges. > > I guess what happened here was I picked up a copy of the MIT license from the > code I sent to perfmon. Would a BSD license be acceptable instead? I > think legal is going to want some kind of license and disclaimer in the file > itself for me to be able to send it out and it would help to have a proposal. > If the only alternative is GPL, they tend to get nervous, but if that is what > is required, so be it. Neither you nor I can change the license without the approval of all copyright holders for that file. I'm afraid you'll have to browbeat legal into being sensible (I know, it's not fun). Perhaps they'd be happier if your *email* containing the patch clearly stated this was being contributed under the GPL? > To my way of thinking, the user should be able to look at the file and find > out what version of the BKDG the file was derived from. That way they can > know whether or not the file has been updated to match a particular revision > of processors. As new processors come out, we can keep the file updated > with the corresponding BKDG version. So it seems to provide useful > information, no? I don't care if it is a changelog entry or not, but I > think the comment provides useful information. I agree, it's useful to document which BKDG version the file corresponds to. Doesn't need to be more than a single line or so, though, I would think. thanks, john |