On Sun, 2007-02-11 at 16:46 -0600, Milton Miller wrote:
> As far as I understand, you are providing access to a completely new
> hardware that is related to the PMU hardware by the fact that it
> collects a program counter. It doesn't use the PMU counters nor the
> PMU event selection.
> In fact, why can the existing op_model_cell profiling not run while
> the SPU profiling runs? Is there a shared debug bus inside the
> chip? Or just the data stream with your buffer_sync code?
There are two reasons you cannot do SPU profiling and profiling on non
SPU events at the sametime. 1) the SPU PC values are routed on the
debug bus. You cannot also route the signals for other non SPU events
on the debug bus since they will conflict. Specifically, the signals
would get logically OR'd on the bus. The exception is PPU cycles which
does not use the debug bus. 2) the hardware that captures the SPU
program counters has some shared components with the HW performance
counters. To use the SPU program counter hardware, the performance
counter hardware must be disabled.
In summary, we cannot do SPU cycle profiling and non SPU event profiling
at the same time due to limitations in the hardware.