From: Egi, Norbert <n.egi@la...>  20071120 16:39:10

Hi, =20 My intention is to measure the number of L2 cache misses on a machine = with two quad core Intel Xeon (X5355) CPUs running a Click software = router in the kernel. I'm setting opcontrol with = event=3DLLC_MISSES:100000:65:1:0 in order to count the L2 misses. This = works fine, but I'm having trouble interpreting the results I get, which = probably comes from that I don't understand what the "count" (which is = set in my current case to 100.000) means and how the sampling works. =20 I played a bit with this count's value and found that if I decrease it = to its 1/10th (i.e. 10.000) then I get roughly 10 times higher numbers = and when I increase it to 10 times higher (i.e. 1.000.000) I get roughly = 10 times lower numbers on L2 cache misses. Thus, I assume the value of = it influences how often the sampling is carried out and therefore has an = important role in the interpretation of the results. The question still = is how I can infer the number of cache misses that occured during = profiling.=20 =20 Any information on this would be greatly appreciated, Norbert =20 