From: William C. <wc...@nc...> - 2004-10-06 15:40:20
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Carl Love wrote: > Will: > > Here is a link to the various architecture books. Last night I verified > that the link is accessible from outside IBM. Sorry it took so long to > send the link. I really wanted to make sure that the web page was > visible from outside IBM. > > http://www-106.ibm.com/developerworks/eserver/articles/archguide.html > > Carl Love > I have these and looked through them. Book III seemed like the best bet, but it refers to a Book IV which wasn't available on the web page. Book III describes the registers in appendix E, but doesn't give any detail about the events or the constraints on the combinations of events. Page 97 of Book III says: The bit definitions of MMCR1 are as follows. MMCR1 bits that are not implemented are treated as reserved. Bit(s) Description 0:4 PMC3 Selector (PMC3SEL) 5:9 PMC4 Selector (PMC4SEL) 10:14 PMC5 Selector (PMC5SEL) 15:19 PMC6 Selector (PMC6SEL) 20:24 PMC7 Selector (PMC7SEL) Each of these fields contains a code (one of at most 32 values) that identifies the event to be counted in PMCs 3 through 7 respectively; see Book IV. For power4+ on page 105 pretty much the same thing: 32:36 PMC3 Selector (PMC3SEL) 37:41 PMC4 Selector (PMC4SEL) 42:46 PMC5 Selector (PMC5SEL) 47:51 PMC6 Selector (PMC6SEL) 52:56 PMC7 Selector (PMC7SEL) 57:61 PMC8 Selector (PMC8SEL) Each of these fields contains a code (one of at most 32 values) that identifies the event to be counted in PMCs 3 through 8 respectively; see Book IV. -Will |