I want to collect L1 cache misses, L2 cache misses and TLB misses. But I don't know which events to use. Can you help me?
The events in oprofile's document (ICACHE_MISSES, DATA_CACHE_ACCESSES, DATA_CACHE_MISSES, DATA_CACHE_REFILLS_FROM_L2) seems do not differentiate L1 and L2 cache.
Another question about the counter field for events:
|The counter reset value, e.g. 100000|
if I set the count of CPU_CLK_UNHALTED to 10000, and oprofile tells CPU_CLK_UNHALTED 1000 samples, does this mean the total cpu cycles used is 1000*10000=10^7?
Thank you all!