From: <nou...@li...> - 2007-04-11 18:22:29
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NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: test.xml Log Message: Implement basic value formatting and named constant retrieval. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/test.xml,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -3 -r1.1.1.1 -r1.2 --- test.xml 9 Apr 2007 10:52:26 -0000 1.1.1.1 +++ test.xml 11 Apr 2007 18:21:57 -0000 1.2 @@ -94,8 +94,8 @@ <!-- first define a "record" as a group --> <group name="controller"> <reg32 name="CMD" offset="0x0" /> - <reg8 name="PARAM1" offset="0x4" /> - <reg8 name="PARAM2" offset="0x5" /> + <reg8 name="PARAM1" offset="0x4" type="int" /> + <reg8 name="PARAM2" offset="0x5" type="uint" /> </group> <!-- then use anonymous array to place these "controllers" around --> <array offset="0x7000" stride="6" length="1"> |
From: <nou...@li...> - 2007-04-14 11:56:55
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NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: test.xml Log Message: Hopefully a proper answer to Question 19. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/test.xml,v retrieving revision 1.2 retrieving revision 1.3 diff -u -3 -r1.2 -r1.3 --- test.xml 11 Apr 2007 18:21:57 -0000 1.2 +++ test.xml 14 Apr 2007 11:56:55 -0000 1.3 @@ -139,5 +139,29 @@ <use-group ref="basic_crtc_regs" /> </variant> +<!-- demonstration of a solution to Question 19 --> +<group name="ramdac_common"> + <stripe name="NV10_PRAMDAC" offset="0x12000" stride="0x1000" + length="2"> + <reg32 name="WIDTH" offset="0x0" /> + <reg32 name="HEIGHT" offset="0x4" /> + <reg32 name="DELAY_ROW" offset="0x20" /> + <reg32 name="DELAY_COL" offset="0x24" /> + </stripe> +</group> +<variant id="10"> + <use-group ref="ramdac_common" /> +</variant> +<variant id="11"> + <use-group ref="ramdac_common" /> + <!-- This stripe def is copied from NV10_PRAMDAC and changed the name + to get variant specific name prefix --> + <stripe name="NV11_PRAMDAC" offset="0x12000" stride="0x1000" + length="2"> + <reg32 name="MASKING" offset="0x10" /> + </stripe> +</variant> + + </database> |
From: <nou...@li...> - 2007-04-15 11:53:46
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NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: test.xml Log Message: Add autoincrementing and unknown reg8/reg32 value types. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/test.xml,v retrieving revision 1.4 retrieving revision 1.5 diff -u -3 -r1.4 -r1.5 --- test.xml 15 Apr 2007 11:30:30 -0000 1.4 +++ test.xml 15 Apr 2007 11:53:47 -0000 1.5 @@ -131,7 +131,9 @@ <translation domain="vga_crtc"> <reg8 offset="0x001d" name="VGA_INDEX" type="offset" /> - <reg8 offset="0x001e" name="VGA_DATA" type="hex" /> + <reg8 offset="0x001e" name="VGA_DATA" /> + <reg8 offset="0x001f" name="VGA_DATA_AUTO" type="autoinc" /> + <reg8 offset="0x001c" name="VGA_DATA_INVA" type="inva" /> </translation> </group> <variant id="30 31 32"> |
From: <nou...@li...> - 2007-04-21 20:50:17
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NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Make RAM amount an unsigned int instead of hex, easier to read. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -3 -r1.1.1.1 -r1.2 --- nvregisters.xml 9 Apr 2007 10:52:26 -0000 1.1.1.1 +++ nvregisters.xml 21 Apr 2007 20:50:17 -0000 1.2 @@ -472,7 +472,8 @@ <use-group ref="nv04_regs" /> <reg32 name="NV04_FIFO_DATA" offset="0x0010020c"> - <bitfield name="NV10_RAM_AMOUNT_MB" high="31" low="20" /> + <bitfield name="NV10_RAM_AMOUNT_MB" high="31" low="20" + type="uint" /> </reg32> <reg32 name="NV10_PGRAPH_DEBUG_4" offset="0x00400090" /> |
From: <nou...@li...> - 2007-05-18 16:16:00
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NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Change NV_PCRTC and NV_PCIO into stripes, as they actually overlapped, which was illegal. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.2 retrieving revision 1.3 diff -u -3 -r1.2 -r1.3 --- nvregisters.xml 21 Apr 2007 20:50:17 -0000 1.2 +++ nvregisters.xml 18 May 2007 16:15:56 -0000 1.3 @@ -563,7 +563,7 @@ length="1" /> - <array name="NV_PCRTC0" offset="0x00600000" stride="0x00002000" + <stripe name="NV_PCRTC" offset="0x00600000" stride="0x00002000" length="2"> <reg32 name="INTR_0" offset="0x100"> @@ -583,7 +583,7 @@ <bitfield name="FPP2" high="16" low="16" /> <bitfield name="FPP1" high="17" low="17" /> </reg32> - </array> + </stripe> <array name="NV_PFIFO" offset="0x00002000" stride="0x00010000" length="1"> @@ -639,7 +639,7 @@ first </array> - <array name="NV_PCIO" offset="0x00601000" stride="0x2000" length="2"> + <stripe name="NV_PCIO" offset="0x00601000" stride="0x2000" length="2"> Presumably this covers both NV_PCIO0 and NV_PCIO1, containing these two CRTC index/data registers. <translation domain="vga_crtc"> @@ -647,7 +647,7 @@ <reg8 name="CRTC_DATA" offset="0x3d5" /> </translation> <reg8 name="CRTC_IN_STAT_1" offset="0x3da" /> - </array> + </stripe> <array name="NV_PDIO0" offset="0x00681000" stride="0x00002000" length="1" /> |
From: <nou...@li...> - 2007-05-18 19:04:34
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NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: test.xml Log Message: Added some more translation fun. Now you can test nested translations! =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/test.xml,v retrieving revision 1.7 retrieving revision 1.8 diff -u -3 -r1.7 -r1.8 --- test.xml 18 May 2007 17:39:34 -0000 1.7 +++ test.xml 18 May 2007 19:04:32 -0000 1.8 @@ -178,6 +178,15 @@ <use-group ref="basic_crtc_regs" /> </variant> +<stripe name="TRANSADDR" offset="0x15000" stride="0x30" length="5"> + <translation domain="bogus_space"> + <reg32 offset="0x0" name="TA_INDEX" type="offset" /> + <reg8 offset="0x4" name="TA_DATA8" /> + <reg32 offset="0x8" name="TA_DATA32" /> + </translation> + <use-group ref="basic_crtc_regs" /> +</stripe> + <!-- demonstration of a solution to Question 19 --> <group name="ramdac_common"> <stripe name="NV10_PRAMDAC" offset="0x12000" stride="0x1000" |
From: <nou...@li...> - 2007-05-19 10:14:01
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NouVeau CVS commit Author : thunderbird Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: vga_crtc-regs.xml Log Message: Add some CRTC locking values =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/vga_crtc-regs.xml,v retrieving revision 1.2 retrieving revision 1.3 diff -u -3 -r1.2 -r1.3 --- vga_crtc-regs.xml 18 May 2007 22:26:50 -0000 1.2 +++ vga_crtc-regs.xml 19 May 2007 10:13:55 -0000 1.3 @@ -37,7 +37,11 @@ <reg8 name="NV_VGA_CRTCX_REPAINT1" offset="0x1a" /> <reg8 name="NV_VGA_CRTCX_FIFO0" offset="0x1b" /> <reg8 name="NV_VGA_CRTCX_FIFO1" offset="0x1c" /> - <reg8 name="NV_VGA_CRTCX_LOCK" offset="0x1f" /> + <reg8 name="NV_VGA_CRTCX_LOCK" offset="0x1f"> + <value name="UNLOCK_RW" value="0x57" /> + <value name="UNLOCK_RO" value="0x75" /> + <value name="LOCK" value="0x99" /> + </reg8> <reg8 name="NV_VGA_CRTCX_FIFO_LWM" offset="0x20" /> <reg8 name="NV_VGA_CRTCX_BUFFER" offset="0x21" /> <reg8 name="NV_VGA_CRTCX_LSR" offset="0x25" /> |
From: <nou...@li...> - 2007-05-19 10:21:05
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NouVeau CVS commit Author : thunderbird Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Prepare for tvout registers =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.6 retrieving revision 1.7 diff -u -3 -r1.6 -r1.7 --- nvregisters.xml 19 May 2007 10:18:27 -0000 1.6 +++ nvregisters.xml 19 May 2007 10:20:31 -0000 1.7 @@ -570,6 +570,11 @@ </array> --> </group> +<group name="tvout_regs"> + <array name="NV_PTV" offset="0x0000d000" stride="0x00001000" length="1"> + </array> +</group> + <group name="common_regs_from_ddx"> <brief>This set of register definitions comes from DDX nvreg.h.</brief> @@ -599,7 +604,7 @@ </reg32> </stripe> - <array name="NV_PFIFO" offset="0x00002000" stride="0x00010000" + <array name="NV_PFIFO" offset="0x00002000" stride="0x00002000" length="1"> <reg32 name="RAMHT" offset="0x210" /> </array> @@ -831,6 +836,7 @@ <use-group ref="nv30_regs" /> <use-group ref="common_regs_from_ddx" /> + <use-group ref="tvout_regs" /> <stripe name="NV_PRAMDAC" offset="0x00680000" stride="0x00002000" length="2"> |
From: <nou...@li...> - 2007-05-19 15:18:30
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NouVeau CVS commit Author : thunderbird Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Add a few more PRAMDAC registers and add a few TVOUT registers =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.8 retrieving revision 1.9 diff -u -3 -r1.8 -r1.9 --- nvregisters.xml 19 May 2007 11:18:47 -0000 1.8 +++ nvregisters.xml 19 May 2007 15:18:31 -0000 1.9 @@ -70,6 +70,8 @@ <reg32 name="CURSOR_DATA_LO" offset="0x324" /> <reg32 name="CURSOR_DATA_HI" offset="0x328" /> + <reg32 name="REG_404" offset="0x404" /> + <reg32 name="NVPLL" offset="0x500" /> <reg32 name="VPLL" offset="0x508" /> @@ -112,7 +114,11 @@ <reg32 name="VPLL_B" offset="0x578" /> <reg32 name="VPLL2_B" offset="0x57c" /> + <reg32 name="REG_580" offset="0x580" /> + <reg32 name="REG_594" offset="0x594" /> + <reg32 name="GENERAL_CONTROL" offset="0x600" /> + <reg32 name="PALETTE_RECOVERY" offset="0x604" /> <reg32 name="TEST_CONTROL" offset="0x608" /> <reg32 name="TEST_DATA" offset="0x610" /> @@ -572,6 +578,8 @@ <group name="tvout_regs"> <array name="NV_PTV" offset="0x0000d000" stride="0x00001000" length="1"> + <reg32 name="TV_INDEX" offset="0x220" /> + <reg32 name="TV_DATA" offset="0x224" /> </array> </group> |
From: <nou...@li...> - 2007-05-19 15:37:24
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NouVeau CVS commit Author : thunderbird Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Add more CRTC regs =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.9 retrieving revision 1.10 diff -u -3 -r1.9 -r1.10 --- nvregisters.xml 19 May 2007 15:18:31 -0000 1.9 +++ nvregisters.xml 19 May 2007 15:37:26 -0000 1.10 @@ -598,6 +598,9 @@ </reg32> <reg32 name="INTR_EN_0" offset="0x140" /> <reg32 name="START" offset="0x800" /> + <reg32 name="CONFIG" offset="0x804" /> + <reg32 name="RASTER" offset="0x808" /> + <reg32 name="CURSOR" offset="0x80c" /> <reg32 name="CURSOR_CONFIG" offset="0x810" /> <reg32 name="CRTC_081C" offset="0x81c" /> <reg32 name="CRTC_0830" offset="0x830" /> |
From: <nou...@li...> - 2007-06-22 11:54:18
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NouVeau CVS commit Author : carlosmn Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Add NV04_PGRAPH_DEBUG_{0..3} =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.10 retrieving revision 1.11 diff -u -3 -r1.10 -r1.11 --- nvregisters.xml 19 May 2007 15:37:26 -0000 1.10 +++ nvregisters.xml 22 Jun 2007 11:54:14 -0000 1.11 @@ -330,6 +330,10 @@ <use-group ref="nv03_regs" /> + <reg32 name="NV04_PGRAPH_DEBUG_0" offset="0x00400080" /> + <reg32 name="NV04_PGRAPH_DEBUG_1" offset="0x00400084" /> + <reg32 name="NV04_PGRAPH_DEBUG_2" offset="0x00400088" /> + <reg32 name="NV04_PGRAPH_DEBUG_3" offset="0x0040008c" /> <reg32 name="NV04_PGRAPH_STATUS" offset="0x00400700" /> <reg32 name="NV04_PGRAPH_CTX_SWITCH1" offset="0x00400160" /> <reg32 name="NV04_PGRAPH_CTX_SWITCH2" offset="0x00400164" /> |
From: <nou...@li...> - 2007-06-22 17:29:25
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NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: test.xml Log Message: Allow anonymous stripes and arrays, even when length>1. This is the answer to question 20. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/test.xml,v retrieving revision 1.9 retrieving revision 1.10 diff -u -3 -r1.9 -r1.10 --- test.xml 19 May 2007 11:13:01 -0000 1.9 +++ test.xml 22 Jun 2007 17:28:55 -0000 1.10 @@ -51,7 +51,9 @@ Except that here we define values directly. </doc> - <value name="true" value="-1" /> + <value name="true" value="-1"> + <brief>a single signed bit, odd, hunh?</brief> + </value> <value name="false" value="0" /> </bitfield> <bitfield name="SWITCH3" high="3" low="2"> @@ -122,6 +124,11 @@ <reg32 name="DATA2" offset="0x18" /> </stripe> +<stripe offset="0x50100" stride="16" length="2"> + <reg32 name="ANON_STRIPE_A" offset="0x0" /> + <reg32 name="ANON_STRIPE_B" offset="0x4" /> +</stripe> + <!-- a special use of array for giving a base address --> <!-- first define a "record" as a group --> <group name="controller"> |
From: <nou...@li...> - 2007-06-22 21:02:22
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NouVeau CVS commit Author : phillipezolt Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: r300_reg.xml Added Files: radeon_pcie_gart.xml Log Message: More database fixups. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/r300_reg.xml,v retrieving revision 1.1 retrieving revision 1.2 diff -u -3 -r1.1 -r1.2 --- r300_reg.xml 21 Jun 2007 14:02:39 -0000 1.1 +++ r300_reg.xml 22 Jun 2007 21:02:20 -0000 1.2 @@ -3,8 +3,8 @@ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> -<domain name="R300" /> +<domain name="R300" /> <enum name="R300_TX_FMT_SWIZZLE"> <value name="R300_TX_FMT_SWIZZLE_X" value="1" /> <value name="R300_TX_FMT_SWIZZLE_Y" value="1" /> @@ -14,6 +14,7 @@ <value name="R300_TX_FMT_SWIZZLE_ONE" value="5" /> </enum> + <variant id="RS480"> <!-- @@ -31,6 +32,16 @@ --> + <translation domain="radeon_pcie_gart"> + <reg32 name="CLOCK_CNTL_INDEX" offset="0x0008" type="offset"> + <bitfield name="RADEON_PLL_WR_EN" high="7" low="7" /> + </reg32> + + <reg32 name="CLOCK_CNTL_DATA" offset="0x000c" access="rw" /> + + </translation> + + <reg32 name="RADEON_BIOS_0_SCRATCH" offset="0x0010"/> <reg32 name="RADEON_BIOS_1_SCRATCH" offset="0x0014"/> <reg32 name="RADEON_BIOS_2_SCRATCH" offset="0x0018"/> @@ -40,6 +51,40 @@ <reg32 name="RADEON_BIOS_6_SCRATCH" offset="0x0028"/> <reg32 name="RADEON_BIOS_7_SCRATCH" offset="0x002C"/> + + <reg32 name="RADEON_BUS_CNTL" offset="0x0030"> + <bitfield name="RADEON_BUS_MASTER_DIS" high="6" low="6" /> + <bitfield name="RADEON_BUS_RD_DISCARD_EN" high="24" low="24" /> + <bitfield name="RADEON_BUS_RD_ABORT_EN" high="25" low="25" /> + <bitfield name="RADEON_BUS_MSTR_DISCONNECT_EN" high="28" low="28" /> + <bitfield name="RADEON_BUS_WRT_BURST" high="29" low="29" /> + <bitfield name="RADEON_BUS_READ_BURST" high="30" low="30" /> + </reg32> + + + <!-- FIXME: We need to do the variant stuff for this: + + <translation domain="radeon_pcie_gart"> + <reg32 name="RADEON_PCIE_INDEX" offset="0x0030" type="offset" > + <bitfield name="WRITE" high="8" low="8" /> + </reg32> + <reg32 name="RADEON_PCIE_DATA" offset="0x0034" access="rw" /> + </translation> + + --> + + <reg32 name="RADEON_CRTC_GEN_CNTL" offset="0x0050"> + <bitfield name="RADEON_CRTC_DBL_SCAN_EN" high="0" low="0" /> + <bitfield name="RADEON_CRTC_INTERLACE_EN" high="1" low="1" /> + <bitfield name="RADEON_CRTC_CSYNC_EN" high="4" low="4" /> + <bitfield name="RADEON_CRTC_ICON_EN" high="15" low="15" /> + <bitfield name="RADEON_CRTC_CUR_EN" high="16" low="16" /> + <bitfield name="RADEON_CRTC_CUR_MODE_MASK" high="23" low="20" /> + <bitfield name="RADEON_CRTC_EXT_DISP_EN" high="24" low="24" /> + <bitfield name="RADEON_CRTC_EN" high="25" low="25" /> + <bitfield name="RADEON_CRTC_DISP_REQ_EN_B" high="26" low="26" /> + </reg32> + <reg32 name="RADEON_RBBM_SOFT_RESET" offset="0x00F0"> <bitfield name="RADEON_SOFT_RESET_CP" high="0" low="0" /> <bitfield name="RADEON_SOFT_RESET_HI" high="1" low="1" /> @@ -81,19 +126,28 @@ <bitfield name="R300_MC_IDLE" high="4" low="4" /> </reg32> - <reg32 name="RADEON_NB_TOM" offset="0x015c" /> - <reg32 name="R300_MC_INIT_MISC_LAT_TIMER" offset="0x0180" > - <bitfield name="MC_CPR_INIT_LAT_SHIFT" high="0" low="0"/> - <bitfield name="MC_VF_INIT_LAT_SHIFT" high="8" low="8"/> - <bitfield name="MC_DISP1R_INIT_LAT_SHIFT" high="12" low="12"/> - <bitfield name="MC_FIXED_INIT_LAT_SHIFT" high="16" low="16"/> - <bitfield name="MC_E2R_INIT_LAT_SHIFT" high="20" low="20"/> - <bitfield name="MC_SAME_PAGE_PRIO_SHIFT" high="24" low="24"/> - <bitfield name="MC_GLOBW_INIT_LAT_SHIFT" high="28" low="28"/> + <reg32 name="R300_MC_INIT_GFX_LAT_TIMER" offset="0x0154" > + <bitfield name="MC_G3D0R_INIT_LAT" high="0" low="0"/> + <bitfield name="MC_G3D1R_INIT_LAT" high="4" low="4"/> + <bitfield name="MC_G3D2R_INIT_LAT" high="8" low="8"/> + <bitfield name="MC_G3D3R_INIT_LAT" high="12" low="12"/> + <bitfield name="MC_TX0R_INIT_LAT" high="16" low="16"/> + <bitfield name="MC_TX1R_INIT_LAT" high="20" low="20"/> + <bitfield name="MC_GLOBR_INIT_LAT" high="24" low="24"/> + <bitfield name="MC_GLOBW_FULL_LAT" high="28" low="28"/> </reg32> - <reg32 name="RADEON_AGP_CNTL" offset="0x0174"> + <reg32 name="RADEON_NB_TOM" offset="0x015c" /> + + <translation domain="radeon_pcie_gart"> + <reg32 name="RADEON_IGPGART_INDEX" offset="0x0168" type="offset" /> + <reg32 name="RADEON_IGPGART_DATA" offset="0x016c" access="rw" /> + </translation> + + + <reg32 name="RADEON_AGP_BASE" offset="0x0170" /> + <reg32 name="RADEON_AGP_CNTL" offset="0x0174"> <bitfield name="RADEON_AGP_APER_SIZE" high="5" low="0"> <value name="RADEON_AGP_APER_SIZE_256MB" value="0" /> <value name="RADEON_AGP_APER_SIZE_128MB" value="0x20" /> @@ -107,7 +161,17 @@ </reg32> - + <reg32 name="R300_MC_INIT_MISC_LAT_TIMER" offset="0x0180" > + <bitfield name="MC_CPR_INIT_LAT" high="0" low="0"/> + <bitfield name="MC_VF_INIT_LAT" high="4" low="4"/> + <bitfield name="MC_DISP0R_INIT_LAT" high="8" low="8"/> + <bitfield name="MC_DISP1R_INIT_LAT" high="12" low="12"/> + <bitfield name="MC_FIXED_INIT_LAT" high="16" low="16"/> + <bitfield name="MC_E2R_INIT_LAT" high="20" low="20"/> + <bitfield name="MC_SAME_PAGE_PRIO" high="24" low="24"/> + <bitfield name="MC_GLOBW_INIT_LAT" high="28" low="28"/> + </reg32> + <reg32 name="RADEON_CRTC_H_TOTAL_DISP" offset="0x0200" > <bitfield name="RADEON_CRTC_H_TOTAL" high="9" low="0" /> <bitfield name="RADEON_CRTC_H_DISP" high="24" low="16" /> @@ -153,6 +217,41 @@ <bitfield name="Select_CRTC2" high="23" low="23" /> </reg32> + + <!-- This is defined in the mplayer headers + From: http://www.gelato.unsw.edu.au/lxr/source/drivers/video/aty/radeon_pm.c + + 1470 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo) + ... + 1505 /* Enable LVDS_PLL */ + 1506 tmp = INREG(LVDS_PLL_CNTL); + 1507 tmp &= ~0x30000; + 1508 tmp |= 0x10000; + 1509 OUTREG(LVDS_PLL_CNTL, tmp); + ... + + 1612 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo) + ... + 1802 /* Set LVDS registers but keep interface & pll down */ + .... + 1805 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); + ... + + int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state) + 2585 /* Switch off LVDS interface */ + 2590 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000); + --> + + <reg32 name="RADEON_LVDS_PLL_CNTL" offset="0x02d4" > + + <bitfield name="STATUS" high="17" low="16" > + <value name="ENABLE" value="1" /> + <value name="DISABLE" value="2"/> + </bitfield> + <bitfield name="HSYNC_DELAY" high="31" low="28" /> + </reg32> + + <reg32 name="RADEON_VGA_DDA_CONFIG" offset="0x02e8" /> <reg32 name="RADEON_VGA_ON_OFF" offset="0x02ec" /> @@ -161,7 +260,6 @@ <reg32 name="RADEON_OV0_BASE_ADDR" offset="0x043c" /> <reg32 name="DISP_PWR_MAN" offset="0x0D08" > - <bitfield name="DISP_PWR_MAN_D3_CRTC_EN" high="0" low="0" /> <bitfield name="DISP2_PWR_MAN_D3_CRTC2_EN" high="4" low="4" /> <bitfield name="DISP_D3_RST" high="16" low="16" /> @@ -182,6 +280,35 @@ <bitfield name="RADEON_CRT2_DISP1_SEL" high="5" low="5" /> </reg32> + + + <reg32 name="RADEON_RBBM_STATUS" offset="0x0E40" > + <bitfield name="RBBM_FIFOCNT" high="6" low="0" /> + <bitfield name="HIRQ_ON_RBB" high="8" low="8" /> + <bitfield name="CPRQ_ON_RBB" high="9" low="9" /> + <bitfield name="CFRQ_ON_RBB" high="10" low="10" /> + <bitfield name="HIRQ_IN_RTBUF" high="11" low="11" /> + <bitfield name="CPRQ_IN_RTBUF" high="12" low="12" /> + <bitfield name="CFRQ_IN_RTBUF" high="13" low="13" /> + <bitfield name="PIPE_BUSY" high="14" low="14" /> + <bitfield name="ENG_EV_BUSY" high="15" low="15" /> + <bitfield name="CP_CMDSTRM_BUSY" high="16" low="16" /> + <bitfield name="E2_BUSY" high="17" low="17" /> + <bitfield name="RB2D_BUSY" high="18" low="18" /> + <bitfield name="RB3D_BUSY" high="19" low="19" /> <!--not used on r300 --> + <bitfield name="VAP_BUSY" high="20" low="20" /> + <bitfield name="RE_BUSY" high="21" low="21" /> <!--not used on r300 --> + <bitfield name="TAM_BUSY" high="22" low="22" /> <!--not used on r300 --> + <bitfield name="TDM_BUSY" high="23" low="23" /> <!--not used on r300 --> + <bitfield name="PB_BUSY" high="24" low="24" /> <!--not used on r300 --> + <bitfield name="TIM_BUSY" high="25" low="25" /> <!--not used on r300 --> + <bitfield name="GA_BUSY" high="26" low="26" /> + <bitfield name="CBA2D_BUSY" high="27" low="27" /> + <bitfield name="RBBM_ACTIVE" high="31" low="31" /> + </reg32> + + + <reg32 name="RADEON_DP_SRC_FRGD_CLR" offset="0x15d8" > <bitfield name="Color" high="31" low="0" /> <!-- RGBA? --> </reg32> |
From: <nou...@li...> - 2007-06-23 15:12:10
|
NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Add more things from DRM register header, and use the new allowed way of using anonymous stripes (fixed the old BUFFERSETUP, which was wrong name). =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.11 retrieving revision 1.12 diff -u -3 -r1.11 -r1.12 --- nvregisters.xml 22 Jun 2007 11:54:14 -0000 1.11 +++ nvregisters.xml 23 Jun 2007 15:12:11 -0000 1.12 @@ -47,9 +47,18 @@ <value name="NV_DMA_ACCESS_RO" value="1" /> <value name="NV_DMA_ACCESS_WO" value="2" /> <value name="NV_DMA_TARGET_VIDMEM" value="0" /> + <value name="NV_DMA_TARGET_PCI" value="2" /> <value name="NV_DMA_TARGET_AGP" value="3" /> </enum> +<enum name="unknown3"> + <value name="NV_CLASS_DMA_FROM_MEMORY" value="0x00000002" /> + <value name="NV_CLASS_DMA_TO_MEMORY" value="0x00000003" /> + <value name="NV_CLASS_NULL" value="0x00000030" /> + <value name="NV_CLASS_DMA_IN_MEMORY" value="0x0000003D" /> +</enum> + + <!-- ***************** BITFIELD SETS ********************************** --> @@ -273,6 +282,16 @@ <reg32 name="NV03_PMC_INTR_EN_0" offset="0x140"> <bitfield name="MASTER_ENABLE" high="0" low="0" /> </reg32> + <reg32 name="NV03_PMC_ENABLE" offset="0x200"> + <bitfield name="PFIFO" high="8" low="8" /> + <bitfield name="PGRAPH" high="12" low="12" /> + <bitfield name="UNK13" high="13" low="13"> + <doc>Disabling this bit breaks newer (G7X only?) + mobile chipsets, the card will hang early on in + the X init process. + </doc> + </bitfield> + </reg32> <reg32 name="NV03_PGRAPH_INTR" offset="0x00400100" /> <reg32 name="NV03_PGRAPH_INTR_EN" offset="0x00400140" /> @@ -486,6 +505,14 @@ <reg32 name="METHOD" offset="0x0" /> <reg32 name="DATA" offset="0x4" /> </array> --> + + <reg32 name="NV04_PTIMER_INTR_0" offset="0x00009100" /> + <reg32 name="NV04_PTIMER_INTR_EN_0" offset="0x00009140" /> + <reg32 name="NV04_PTIMER_NUMERATOR" offset="0x00009200" /> + <reg32 name="NV04_PTIMER_DENOMINATOR" offset="0x00009210" /> + <reg32 name="NV04_PTIMER_TIME_0" offset="0x00009400" /> + <reg32 name="NV04_PTIMER_TIME_1" offset="0x00009410" /> + <reg32 name="NV04_PTIMER_ALARM_0" offset="0x00009420" /> </group> <group name="nv10_regs"> @@ -560,6 +587,13 @@ What all should this include from the previous groups? </doc> + <reg32 name="NV40_PMC_1700" offset="0x00001700"> + <brief>How does this relate to NV_PMC?</brief> + </reg32> + <reg32 name="NV40_PMC_1704" offset="0x00001704" /> + <reg32 name="NV40_PMC_1708" offset="0x00001708" /> + <reg32 name="NV40_PMC_170C" offset="0x0000170C" /> + <reg32 name="NV40_PGRAPH_INTR_EN" offset="0x0040013C"> <bitfield name="NOTIFY" high="0" low="0" /> <bitfield name="MISSING_HW" high="4" low="4" /> @@ -644,8 +678,7 @@ <reg32 name="BUFFER" offset="0x700" /> <reg32 name="STOP" offset="0x704" /> - <stripe name="BUFFERSETUP" offset="0x900" stride="0x4" - length="2"> + <stripe offset="0x900" stride="0x4" length="2"> <reg32 name="BASE" offset="0x00" /> <reg32 name="LIMIT" offset="0x08" /> <reg32 name="LUMINANCE" offset="0x10" /> @@ -777,12 +810,19 @@ <reg32 name="CURSYNC" offset="0x404" /> </array> - <array name="NV_PFB" offset="0x00100000" stride="0x00001000" + <array name="NV10_PFB" offset="0x00100000" stride="0x00001000" length="1"> <use-group ref="common_pfb_regs" /> - <reg32 name="TILE_NV10" offset="0x240" /> +<!-- <reg32 name="TILE_NV10" offset="0x240" /> <reg32 name="TILE_SIZE_NV10" offset="0x244" /> +conflicting DDX definition --> + <stripe offset="0x240" stride="16" length="8"> + <reg32 name="TILE" offset="0x0" /> + <reg32 name="TLIMIT" offset="0x4" /> + <reg32 name="TSIZE" offset="0x8" /> + <reg32 name="TSTATUS" offset="0xc" /> + </stripe> </array> </variant> |
From: <nou...@li...> - 2007-06-24 11:45:42
|
NouVeau CVS commit Author : carlosmn Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Add NV03_PBUS_DEBUG_{0,1} =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.12 retrieving revision 1.13 diff -u -3 -r1.12 -r1.13 --- nvregisters.xml 23 Jun 2007 15:12:11 -0000 1.12 +++ nvregisters.xml 24 Jun 2007 11:45:39 -0000 1.13 @@ -292,7 +292,47 @@ </doc> </bitfield> </reg32> - + + <reg32 name="NV03_PBUS_DEBUG_0" offset="0x0001080"> + <bitfield name="MODE" high="0" low="0" /> + <bitfield name="DESKEWER" high="4" low="4"> + <value name="ENABLED" value="0" /> + <value name="DISABLED" value="1" /> + </bitfield> + <bitfield name="FBIO_SCLK_DELAY" high="11" low="8" /> + <bitfield name="FBIO_FBCLK_DELAY" high="15" low="12" /> + </reg32> + <reg32 name="NV03_PBUS_DEBUG_1" offset="0x0001084"> + <bitfield name="PCIM_THROTTLE" high="0" low="0" /> + <bitfield name="PCIM_CMD" high="1" low="1"> + <value name="SIZE_BASED" value="0" /> + <value name="MRL_ONLY" value="1" /> + </bitfield> + <bitfield name="PCIM_AGP" high="2" low="2"> + <value name="IS_AGP" value="0" /> + <value name="IS_PCI" value="1" /> + </bitfield> + <bitfield name="AGPM_CMD" high="4" low="3"> + <value name="HP_ON_1ST" value="0" /> + <value name="LP_ONLY" value="1" /> + <value name="HP_ONLY" value="2" /> + </bitfield> + <bitfield name="PCIS_WRITE" high="5" low="5"> + <value name="0_CYCLE" value="0" /> + <value name="1_CYCLE" value="1" /> + </bitfield> + <bitfield name="PCIS_2_1" high="6" low="6" /> + <bitfield name="PCIS_RETRY" high="7" low="7" /> + <bitfield name="PCIS_RD_BURST" high="8" low="8" /> + <bitfield name="PCIS_WR_BURST" high="9" low="9" /> + <bitfield name="PCIS_EARLY_RTY" high="10" low="10" /> + <bitfield name="PCIS_RMAIO" high="11" low="11" /> + <bitfield name="PCIS_CPUQ" high="12" low="12" /> + <bitfield name="PCIS_DPSH_PIPE" high="13" low="13" /> + <bitfield name="PCIS_SPARE1" high="14" low="14" /> + <bitfield name="PCIS_SPARE2" high="15" low="15" /> + <bitfield name="PCIS_SPARE3" high="16" low="16" /> + </reg32> <reg32 name="NV03_PGRAPH_INTR" offset="0x00400100" /> <reg32 name="NV03_PGRAPH_INTR_EN" offset="0x00400140" /> <reg32 name="NV03_PGRAPH_CTX_CONTROL" offset="0x00400190" /> |
From: <nou...@li...> - 2007-06-25 15:14:01
|
NouVeau CVS commit Author : carlosmn Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Add a few NV03_PFIFO regs =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.15 retrieving revision 1.16 diff -u -3 -r1.15 -r1.16 --- nvregisters.xml 25 Jun 2007 08:39:58 -0000 1.15 +++ nvregisters.xml 25 Jun 2007 15:13:56 -0000 1.16 @@ -373,7 +373,13 @@ <reg32 name="NV03_PGRAPH_ABS_UCLIPA_YMAX" offset="0x0040056C" /> <reg32 name="NV03_PGRAPH_MONO_COLOR0" offset="0x00400600" /> - <reg32 name="NV03_PFIFO_INTR_0" offset="0x00002100" /> + <reg32 name="NV03_PFIFO_INTR_0" offset="0x00002100"> + <bitfield name="CACHE_ERROR" high="0" low="0" /> + <bitfield name="RUNOUT" high="4" low="4" /> + <bitfield name="RUNOUT_OVERFLOW" high="8" low="8" /> + <bitfield name="DMA_PUSHER" high="12" low="12" /> + <bitfield name="DMA_PTE" high="16" low="16" /> + </reg32> <reg32 name="NV03_PFIFO_INTR_EN_0" offset="0x00002140"> <bitfield name="CACHE_ERROR" high="0" low="0" /> <bitfield name="RUNOUT" high="4" low="4" /> @@ -383,17 +389,67 @@ <bitfield name="SEMAPHORE" high="20" low="20" /> <bitfield name="ACQUIRE_TIMEOUT" high="24" low="24" /> </reg32> - <reg32 name="NV03_PFIFO_RAMHT" offset="0x00002210" /> - <reg32 name="NV03_PFIFO_RAMFC" offset="0x00002214" /> - <reg32 name="NV03_PFIFO_RAMRO" offset="0x00002218" /> - <reg32 name="NV03_PFIFO_CACHES" offset="0x00002500" /> - <reg32 name="NV03_PFIFO_CACHE0_PUSH0" offset="0x00003000" /> - <reg32 name="NV03_PFIFO_CACHE0_PULL0" offset="0x00003040" /> - <reg32 name="NV03_PFIFO_CACHE1_PUSH0" offset="0x00003200" /> - <reg32 name="NV03_PFIFO_CACHE1_PUSH1" offset="0x00003204" /> - <reg32 name="NV03_PFIFO_CACHE1_PULL0" offset="0x00003240" /> - <reg32 name="NV03_PFIFO_CACHE1_PULL1" offset="0x00003250" /> - <reg32 name="NV03_PFIFO_CACHE1_GET" offset="0x00003270" /> + <reg32 name="NV03_PFIFO_RAMHT" offset="0x00002210"> + <bitfield name="BASE_ADDRESS" high="15" low="12" /> + <bitfield name="SIZE" high="17" low="16"> + <value name="4K" value="0" /> + <value name="8K" value="1" /> + <value name="16K" value="2" /> + <value name="32K" value="3" /> + </bitfield> + </reg32> + <reg32 name="NV03_PFIFO_CONFIG_0" offset="0x00002200" /> + <reg32 name="NV03_PFIFO_RAMFC" offset="0x00002214"> + <bitfield name="BASE_ADDRESS" high="15" low="9" /> + </reg32> + <reg32 name="NV03_PFIFO_RAMRO" offset="0x00002218"> + <bitfield name="BASE_ADDRESS" high="15" low="9" /> + <bitfield name="SIZE" high="16" low="16"> + <value name="512" value="0" /> + <value name="8K" value="1" /> + </bitfield> + </reg32> + <reg32 name="NV03_PFIFO_RUNOUT_STATUS" offset="0x00002400" /> + <reg32 name="NV03_PFIFO_RUNOUT_PUT" offset="0x00002410" /> + <reg32 name="NV03_PFIFO_RUNOUT_GET" offset="0x00002420" /> + <reg32 name="NV03_PFIFO_CACHES" offset="0x00002500"> + <bitfield name="REASSIGN" high="0" low="0" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE0_PUSH0" offset="0x00003000"> + <bitfield name="ACCESS" high="0" low="0" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE0_PUSH1" offset="0x00003004"> + <bitfield name="CHID" high="6" low="0" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE0_PULL0" offset="0x00003040"> + <bitfield name="ACCESS" high="0" low="0" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE1_PUSH0" offset="0x00003200"> + <bitfield name="ACCESS" high="0" low="0" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE1_PUSH1" offset="0x00003204"> + <bitfield name="CHID" high="6" low="0" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE1_PUT" offset="0x00003210"> + <bitfield name="ADDRESS" high="6" low="2" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE1_DMA0" offset="0x00003220" /> + <reg32 name="NV03_PFIFO_CACHE1_DMA1" offset="0x00003224" /> + <reg32 name="NV03_PFIFO_CACHE1_DMA2" offset="0x00003228" /> + <reg32 name="NV03_PFIFO_CACHE1_PULL0" offset="0x00003240"> + <bitfield name="ACCESS" high="0" low="0" /> + </reg32> + <reg32 name="NV03_PFIFO_CACHE1_PULL1" offset="0x00003250"> + <bitfield name="CTX" high="4" low="4"> + <value name="CLEAN" value="0" /> + <value name="DIRTY" value="1" /> + </bitfield> + </reg32> + <reg32 name="NV03_PFIFO_CACHE1_GET" offset="0x00003270"> + <bitfield name="ADDRESS" high="6" low="2" /> + </reg32> + <array name="NV03_PFIFO_CACHE1_CTX" offset="0x00003280" + stride="0x10" length="8" /> </group> <group name="nv04_regs"> |
From: <nou...@li...> - 2007-06-25 19:34:23
|
NouVeau CVS commit Author : phillipezolt Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: r300_reg.xml Log Message: Added some TV DAC stuff, and some other random registers. Trying to make my RS480 trace make sense. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/r300_reg.xml,v retrieving revision 1.3 retrieving revision 1.4 diff -u -3 -r1.3 -r1.4 --- r300_reg.xml 24 Jun 2007 01:53:21 -0000 1.3 +++ r300_reg.xml 25 Jun 2007 19:34:23 -0000 1.4 @@ -85,6 +85,49 @@ <bitfield name="RADEON_CRTC_DISP_REQ_EN_B" high="26" low="26" /> </reg32> + + <reg32 name="DAC_CNTL" offset="0x0058"> + <bitfield name="DAC_RANGE" high="1" low="0" > + <value name="PAL" value="0" /> + <value name="NTSC" value="1" /> + <value name="PS2" value="2" /> + </bitfield> + + <bitfield name="DAC_BLANKING" high="2" low="2" /> + <bitfield name="DAC_CMP_EN" high="3" low="3" /> + <bitfield name="DAC_CMP_OUTPUT" high="7" low="7" /> + <bitfield name="DAC_8BIT_EN" high="8" low="8" /> + <bitfield name="DAC_4BPP_PIX_ORDER" high="9" low="9" /> + + <bitfield name="DAC_VGA_ADR_EN" high="13" low="13" /> + <bitfield name="DAC_EXPAND_MODE" high="14" low="14" /> + <bitfield name="DAC_PDWN" high="15" low="15" /> + <bitfield name="DAC_CRC_EN" high="19" low="19" /> + <bitfield name="DAC_MASK_ALL" high="31" low="24" /> + + </reg32> + + + <!-- + from: drivers/video/aty/radeon_pm.c + static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo) + + OUTREG(GPIO_MONID, 0x00030000); + --> + + <reg32 name="GPIO_MONID" offset="0x0068"> + <bitfield name="DISABLE" high="17" low="16" /> + </reg32> + + + <reg32 name="DAC_CNTL2" offset="0x007c"> + <bitfield name="DAC2_EXPAND_MODE" high="14" low="14" /> + <bitfield name="DAC2_CMP_EN" high="7" low="7" /> + <bitfield name="DAC2_PALETTE_ACCESS_CNTL" high="5" low="5" /> + + </reg32> + + <reg32 name="RADEON_RBBM_SOFT_RESET" offset="0x00F0"> <bitfield name="RADEON_SOFT_RESET_CP" high="0" low="0" /> <bitfield name="RADEON_SOFT_RESET_HI" high="1" low="1" /> @@ -117,8 +160,8 @@ <reg32 name="RADEON_MC_AGP_LOCATION" offset="0x014c"> - <bitfield name="fb_location" high="15" low="0" /> - <bitfield name="gart_vm_start" high="31" low="16" /> + <bitfield name="Aper_Start" high="15" low="0" /> + <bitfield name="Aper_End" high="31" low="16" /> </reg32> <reg32 name="RADEON_MC_STATUS" offset="0x0150"> @@ -197,10 +240,44 @@ </reg32> + <reg32 name="RADEON_CRTC_VLINE_CRNT_VLINE" offset="0x0210" > <bitfield name="RADEON_CRTC_CRNT_VLINE_MASK" high="26" low="16" /> </reg32> - + + + <reg32 name="CRTC_OFFSET" offset="0x0224" /> + + <reg32 name="FP_GEN_CNTL" offset="0x0284" > + <bitfield name="FP_FPON" high="0" low="0" /> + <bitfield name="FP_TMDS_EN" high="2" low="2" /> + <bitfield name="FP_PANEL_FORMAT" high="3" low="3" /> + <bitfield name="FP_EN_TMDS" high="7" low="7" /> + <bitfield name="FP_DETECT_SENSE" high="8" low="8" /> + <bitfield name="R200_FP_SOURCE_SEL" high="11" low="10"> + <value name="CRTC1" value="0" /> + <value name="CRTC2" value="1" /> + <value name="RMX" value="2" /> + <value name="TRANS" value="3" /> + </bitfield> + <bitfield name="FP_SEL" high="13" low="13"> + <value name="CRTC1" value="0" /> + <value name="CRTC2" value="1" /> + </bitfield> + <bitfield name="FP_USE_VGA_HSYNC" high="14" low="14" /> + + <bitfield name="FP_CRTC_DONT_SHADOW_HPAR" high="15" low="15" /> + <bitfield name="FP_CRTC_DONT_SHADOW_VPAR" high="16" low="16" /> + <bitfield name="FP_CRTC_DONT_SHADOW_HEND" high="17" low="17" /> + <bitfield name="FP_CRTC_USE_SHADOW_VEND" high="18" low="18" /> + <bitfield name="FP_RMX_HVSYNC_CONTROL_EN" high="20" low="20" /> + <bitfield name="FP_DFP_SYNC_SEL" high="21" low="21" /> + <bitfield name="FP_CRTC_LOCK_8DOT" high="22" low="22" /> + <bitfield name="FP_CRT_SYNC_SEL" high="23" low="23" /> + <bitfield name="FP_USE_SHADOW_EN" high="24" low="24" /> + <bitfield name="FP_CRT_SYNC_ALT" high="26" low="26" /> + + </reg32> <!-- This is defined in the mplayer headers --> @@ -259,6 +336,85 @@ <reg32 name="RADEON_DISPLAY2_BASE_ADDR" offset="0x033c" /> <reg32 name="RADEON_OV0_BASE_ADDR" offset="0x043c" /> + <!-- + 933 /* TV_DAC_CNTL constants */ + 934 #define TV_DAC_CNTL_BGSLEEP 0x00000040 + 935 #define TV_DAC_CNTL_DETECT 0x00000010 + + 936 #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 + 937 #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 + 938 #define TV_DAC_CNTL_BGADJ__SHIFT 16 + 939 #define TV_DAC_CNTL_DACADJ__SHIFT 20 + 940 #define TV_DAC_CNTL_RDACPD 0x01000000 + 941 #define TV_DAC_CNTL_GDACPD 0x02000000 + 942 #define TV_DAC_CNTL_BDACPD 0x04000000 + + With more from: http://www.botchco.com/alex/radeon/hy0/XORG_Radeon_Update_AllInOne.diff + + --> + + <reg32 name="TV_DAC_CNTL" offset="0x088c"> + <bitfield name="NBLANK" high="0" low="0" /> + <bitfield name="NHOLD" high="1" low="1" /> + <bitfield name="DETECT" high="4" low="4" /> + <bitfield name="BGSLEEP" high="6" low="6" /> + + <bitfield name="STD" high="9" low="8" > + <value name="PS2" value="2" /> + </bitfield> + + <bitfield name="BGADJ" high="19" low="16" /> + <bitfield name="DACADJ" high="23" low="20" /> + + <bitfield name="RDACPD" high="24" low="24" /> + <bitfield name="GDACPD" high="25" low="25" /> + <bitfield name="BDACPD" high="26" low="26" /> + + <!-- + <bitfield name="R420_RDACPD" high="25" low="25" /> + <bitfield name="R420_GDACPD" high="26" low="26" /> + <bitfield name="R420_BDACPD" high="27" low="27" /> + --> + <bitfield name="R420_TVENABLE" high="28" low="28" /> + + </reg32> + + + <reg32 name="RADEON_SURFACE_CNTL" offset="0x0B00" > + <bitfield name="RADEON_SURF_TRANSLATION_DIS" high="8" low="8" /> + <bitfield name="RADEON_NONSURF_AP0_SWP" high="21" low="20"> + <value name="LITTLE" value="0" /> + <value name="BIG_16" value="1" /> + <value name="BIG_32" value="2" /> + </bitfield> + <bitfield name="RADEON_NONSURF_AP1_SWP" high="23" low="22"> + <value name="LITTLE" value="0" /> + <value name="BIG_16" value="1" /> + <value name="BIG_32" value="2" /> + </bitfield> + </reg32> + + + <array name="RADEON_SURFACE" offset="0x0B04" stride="0x10" length="8"> + <reg32 name="LOWER_BOUND" offset="0x0" > + </reg32> + + <reg32 name="UPPER_BOUND" offset="0x4" > + </reg32> + + <reg32 name="INFO" offset="0x8" > + <bitfield name="RADEON_SURF_PITCHSEL" high="8" low="0" /> + <bitfield name="RADEON_SURF_TILE_MODE" high="17" low="16"> + <value name="MODE_MACRO" value="0" /> + <value name="MODE_MICRO" value="1" /> + <value name="MODE_32BIT_Z" value="2" /> + <value name="MODE_16BIT_Z" value="3" /> + </bitfield> + </reg32> + + </array> + + <reg32 name="DISP_PWR_MAN" offset="0x0D08" > <bitfield name="DISP_PWR_MAN_D3_CRTC_EN" high="0" low="0" /> <bitfield name="DISP2_PWR_MAN_D3_CRTC2_EN" high="4" low="4" /> @@ -322,6 +478,28 @@ <reg32 name="RADEON_GUI_SCRATCH_REG2" offset="0x15e8" /> <reg32 name="RADEON_GUI_SCRATCH_REG3" offset="0x15ec" /> <reg32 name="RADEON_GUI_SCRATCH_REG4" offset="0x15f0" /> + + <!-- + From: radeon_accelfuncs.c + static void + FUNC_NAME(RADEONSetupForSolidFill)(ScrnInfoPtr pScrn, + int color, + int rop, + unsigned int planemask) + { + .... + if (info->ChipFamily >= CHIP_FAMILY_RV200) { + BEGIN_ACCEL(1); + OUT_ACCEL_REG(RADEON_DST_LINE_PATCOUNT,0x55 << RADEON_BRES_CNTL_SHIFT); + FINISH_ACCEL(); + } + ... + + --> + <reg32 name="RADEON_DST_LINE_PATCOUNT" offset="0x1608" > + <bitfield name="BRES_CNTL" high="16" low="8" /> + </reg32> + <reg32 name="RADEON_DP_WRITE_MASK" offset="0x16cc" /> <reg32 name="RADEON_DEFAULT_OFFSET" offset="0x16e0" /> @@ -593,6 +771,23 @@ <bitfield name="TC6" high="16" low="16" /> <bitfield name="TC7" high="17" low="17" /> </reg32> + + <!-- + + /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between + * rendering commands and overwriting vertex program parameters. + * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and + * avoids bugs caused by still running shaders reading bad data from memory. + */ + #define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ + + OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); + --> + + + <reg32 name="RADEON_SE_TCL_STATE_FLUSH" offset="0x2284"/> + + <!-- From RADEONEngineRestore (where this code is used: @@ -608,6 +803,7 @@ <reg32 name="RADEON_RB2D_DSTCACHE_MODE" offset="0x3428"/> + <reg32 name="R300_GB_ENABLE" offset="0x4008"> <bitfield name="POINT_ENABLE" high="0" low="0" /> <bitfield name="LINE_ENABLE" high="1" low="1" /> |
From: <nou...@li...> - 2007-06-25 22:27:56
|
NouVeau CVS commit Author : carlosmn Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Add some NV03_PMC bitfields =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.16 retrieving revision 1.17 diff -u -3 -r1.16 -r1.17 --- nvregisters.xml 25 Jun 2007 15:13:56 -0000 1.16 +++ nvregisters.xml 25 Jun 2007 22:27:57 -0000 1.17 @@ -286,15 +286,33 @@ <reg32 name="NV03_PMC_BOOT_0" offset="0x0" /> <reg32 name="NV03_PMC_INTR_0" offset="0x100"> - <bitfield name="PFIFO_PENDING" high="8" low="8" /> - <bitfield name="PGRAPH_PENDING" high="12" low="12" /> - <bitfield name="CRTC0_PENDING" high="24" low="24" /> - <bitfield name="CTRC1_PENDING" high="25" low="25" /> - </reg32> - <reg32 name="NV03_PMC_INTR_EN_0" offset="0x140"> - <bitfield name="MASTER_ENABLE" high="0" low="0" /> + <bitfield name="PAUDIO" high="0" low="0" /> + <bitfield name="PMEDIA" high="4" low="4" /> + <bitfield name="PFIFO" high="8" low="8" /> + <bitfield name="PGRAPH0" high="12" low="12" /> + <bitfield name="PGRAPH1" high="13" low="13" /> + <bitfield name="PVIDEO" high="16" low="16" /> + <bitfield name="PTIMER" high="20" low="20" /> + <bitfield name="PFB" high="24" low="24" /> + <bitfield name="PBUS" high="28" low="28" /> + <bitfield name="SOFTWARE" high="31" low="31" /> + </reg32> + <reg32 name="NV03_INTR_EN_0" offset="0x00000140"> + <bitfield name="INTA" high="1" low="0"> + <value name="DISABLED" value="0" /> + <value name="HARDWARE" value="1" /> + <value name="SOFTWARE" value="2" /> + </bitfield> + </reg32> + <reg32 name="NV03_PMC_INTR_READ_0" offset="0x00000160"> + <bitfield name="INTA" high="1" low="0"> + <value name="LOW" value="0" /> + <value name="HIGH" value="1" /> + </bitfield> </reg32> <reg32 name="NV03_PMC_ENABLE" offset="0x200"> + <bitfield name="PAUDIO" high="0" low="0" /> + <bitfield name="PMEDIA" high="4" low="4" /> <bitfield name="PFIFO" high="8" low="8" /> <bitfield name="PGRAPH" high="12" low="12" /> <bitfield name="UNK13" high="13" low="13"> @@ -303,6 +321,12 @@ the X init process. </doc> </bitfield> + <bitfield name="PPMI" high="16" low="16" /> + <bitfield name="PFB" high="20" low="20" /> + <bitfield name="PCRTC" high="24" low="24" /> + <bitfield name="PVIDEO" high="28" low="28" /> + <bitfield name="PFIFO" high="8" low="8" /> + </reg32> <reg32 name="NV03_PBUS_DEBUG_0" offset="0x0001080"> |
From: <nou...@li...> - 2007-06-27 18:58:13
|
NouVeau CVS commit Author : phillipezolt Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: r300_reg.xml Log Message: More registers... =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/r300_reg.xml,v retrieving revision 1.4 retrieving revision 1.5 diff -u -3 -r1.4 -r1.5 --- r300_reg.xml 25 Jun 2007 19:34:23 -0000 1.4 +++ r300_reg.xml 27 Jun 2007 18:58:08 -0000 1.5 @@ -141,6 +141,14 @@ <reg32 name="RADEON_CONFIG_MEMSIZE" offset="0x00F8"/> + <reg32 name="RADEON_CONFIG_APER_SIZE" offset="0x0108"/> + + + <reg32 name="RADEON_HOST_PATH_CNTL" offset="0x0130"> + <bitfield name="APER_CNTL" high="23" low="23" /> + <bitfield name="SOFT_RESET" high="26" low="26" /> + <bitfield name="WC_TIMEOUT_28BCLK" high="30" low="28" /> + </reg32> <reg32 name="RADEON_MEM_CNTL" offset="0x0140"> <!-- @@ -336,7 +344,98 @@ <reg32 name="RADEON_DISPLAY2_BASE_ADDR" offset="0x033c" /> <reg32 name="RADEON_OV0_BASE_ADDR" offset="0x043c" /> - <!-- + <reg32 name="RADEON_CP_RB_BASE" offset="0x0700" > + <doc> + CP_RB_BASE 0x0214 0x00000000 + Bits Mnemonic Meaning + 0-1 + 2-23 rb_base Base address of ring buffer + 24-31 + + NOTE: This address is in the cards address space. + + It is very possible that this address is in memory + mapped by the card's GART. + + </doc> + </reg32> + + <reg32 name="RADEON_CP_RB_CNTL" offset="0x0704" > + + <doc> + From: http://www.handhelds.org/moin/moin.cgi/w100MMRegisters + + Name Address Init value + CP_RB_CNTL 0x0210 0x00000000 + Bits Mnemonic Meaning + 0-5 rb_bufsz Size of the ring buffer in DWORDS, represented as a power of 2 + 6-7 + 8-13 rb_blksz + 14-15 + 16-17 buf_swap + 18-19 max_fetch + 20-26 + 27 rb_no_update + 28-30 + 31 rb_rptr_wr_ena Enable updating of RPTR in system memory?? + + </doc> + <bitfield name="rb_bufsz" high="5" low="0" > + <doc> Size of the ring buffer in DWORDS, represented as a power of 2 </doc> + </bitfield> + <bitfield name="rb_blksz" high="13" low="8" /> + <bitfield name="RADEON_BUF_SWAP" high="17" low="16" > + <value name="RADEON_BUF_SWAP_32BIT" value="2" /> + </bitfield> + <bitfield name="max_fetch" high="18" low="19" /> + <bitfield name="RADEON_RB_NO_UPDATE" high="27" low="27" > + <doc> Enable updating of RPTR in system memory?? </doc> + </bitfield> + + </reg32> + + + + + + <reg32 name="RADEON_CP_RB_RPTR_ADDR" offset="0x070c" > + <doc> + CP_RB_RPTR_ADDR 0x0218 0x00000000 + Bits Mnemonic Meaning + 0-1 rb_rptr_swap + 2-23 rb_rptr_addr + 24-31 + </doc> + <bitfield name="rb_rptr_swap" high="1" low="0" /> + <bitfield name="rb_rptr_addr" high="23" low="2" /> + + </reg32> + + <reg32 name="RADEON_CP_RB_RPTR" offset="0x0710" > + <doc> + CP_RB_RPTR 0x021C 0x00000000 + Bits Mnemonic Meaning + 0-22 rb_rptr Command FIFO read pointer + 23-31 + </doc> + <bitfield name="rb_rptr" high="22" low="0" /> + </reg32> + + + + <reg32 name="RADEON_CP_RB_WPTR" offset="0x0714" > + <doc> + Name Address Init value + CP_RB_WPTR 0x0220 0x00000000 + Bits Mnemonic Meaning + 0-22 rb_wptr + 23-31 + </doc> + <bitfield name="rb_wptr" high="22" low="0" /> + </reg32> + + <reg32 name="TV_DAC_CNTL" offset="0x088c"> + <doc> 933 /* TV_DAC_CNTL constants */ 934 #define TV_DAC_CNTL_BGSLEEP 0x00000040 935 #define TV_DAC_CNTL_DETECT 0x00000010 @@ -350,10 +449,8 @@ 942 #define TV_DAC_CNTL_BDACPD 0x04000000 With more from: http://www.botchco.com/alex/radeon/hy0/XORG_Radeon_Update_AllInOne.diff - - --> + </doc> - <reg32 name="TV_DAC_CNTL" offset="0x088c"> <bitfield name="NBLANK" high="0" low="0" /> <bitfield name="NHOLD" high="1" low="1" /> <bitfield name="DETECT" high="4" low="4" /> @@ -436,6 +533,31 @@ <bitfield name="RADEON_CRT2_DISP1_SEL" high="5" low="5" /> </reg32> + <reg32 name="RADEON_DISP_OUTPUT_CNTL" offset="0x0D64" > + <bitfield name="RADEON_DISP_DAC_SOURCE" high="1" low="0" > + <value name="SOURCE_CRTC" value="0" /> + <value name="SOURCE_CRTC2" value="1" /> + </bitfield> + <bitfield name="RADEON_DISP_TVDAC_SOURCE_CRTC" high="3" low="2" > + <value name="SOURCE_CRTC" value="0" /> + <value name="SOURCE_CRTC2" value="1" /> + </bitfield> + + <!-- + <bitfield name="RADEON_DISP_DAC2_SOURCE" high="3" low="2" > + <value name="SOURCE_CRTC" value="0" /> + <value name="SOURCE_CRTC2" value="1" /> + </bitfield> + --> + + + <bitfield name="RADEON_DISP_TV_SOURCE" high="16" low="16" > + <value name="SOURCE_CRTC" value="0" /> + <value name="SOURCE_CRTC2" value="1" /> + </bitfield> + + </reg32> + <reg32 name="RADEON_RBBM_STATUS" offset="0x0E40" > @@ -464,6 +586,15 @@ </reg32> + <reg32 name="RADEON_DST_PITCH" offset="0x1408" > + </reg32> + + <reg32 name="RADEON_DP_BRUSH_BKGD_CLR" offset="0x1478" > + </reg32> + + <reg32 name="RADEON_DP_BRUSH_FRGD_CLR" offset="0x147C" > + </reg32> + <reg32 name="RADEON_DP_SRC_FRGD_CLR" offset="0x15d8" > <bitfield name="Color" high="31" low="0" /> <!-- RGBA? --> @@ -500,6 +631,101 @@ <bitfield name="BRES_CNTL" high="16" low="8" /> </reg32> + + + <!-- + DST_X_RIGHT_TO_LEFT 0x00000000 + DST_X_LEFT_TO_RIGHT 0x00000001 + + DST_Y_BOTTOM_TO_TOP 0x00000000 + DST_Y_TOP_TO_BOTTOM 0x00000002 + + DST_X_MAJOR 0x00000000 + DST_Y_MAJOR 0x00000004 + + DST_X_TILE 0x00000008 + DST_Y_TILE 0x00000010 + DST_LAST_PEL 0x00000020 + + DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 + DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 + + DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 + DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 + + DST_BRES_SIGN 0x00000100 + DST_HOST_BIG_ENDIAN_EN 0x00000200 + DST_POLYLINE_NONLAST 0x00008000 + DST_RASTER_STALL 0x00010000 + DST_POLY_EDGE 0x00040000 + + + --> + <reg32 name="RADEON_DP_CNTL" offset="0x16c0" > + <bitfield name="DST_X" high="0" low="0"> + <value name="RIGHT_TO_LEFT" value="0" /> + <value name="LEFT_TO_RIGHT" value="1" /> + </bitfield> + + <bitfield name="DST_Y" high="1" low="1"> + <value name="BOTTOM_TO_TOP" value="0" /> + <value name="TOP_TO_BOTTOM" value="1" /> + </bitfield> + + <bitfield name="DST" high="2" low="2"> + <value name="X_MAJOR" value="0" /> + <value name="Y_MAJOR" value="1" /> + </bitfield> + + <bitfield name="DST_X_TILE" high="3" low="3"/> + <bitfield name="DST_Y_TILE" high="4" low="4"/> + <bitfield name="DST_LAST_PEL" high="5" low="5"/> + + <bitfield name="DST_TRAIL" high="6" low="6"> + <value name="X_RIGHT_TO_LEFT" value="0" /> + <value name="X_LEFT_TO_RIGHT" value="1" /> + </bitfield> + + <bitfield name="DST_TRAP" high="7" low="7"> + <value name="FILL_RIGHT_TO_LEFT" value="0" /> + <value name="FILL_LEFT_TO_RIGHT" value="1" /> + </bitfield> + + <bitfield name="DST_BRES_SIGN" high="8" low="8"/> + <bitfield name="DST_HOST_BIG_ENDIAN_EN" high="9" low="9"/> + <bitfield name="DST_POLYLINE_NON_LAST" high="15" low="15"/> + <bitfield name="DST_RASTER_STALL" high="16" low="16"/> + <bitfield name="DST_POLY_EDGE" high="18" low="18"/> + + </reg32> + + + + + + <reg32 name="RADEON__AUX_SC_CNTL" offset="0x1660" > + <bitfield name="AUX1_SC_EN" high="0" low="0" /> + <bitfield name="AUX1_SC_MODE" high="1" low="1"> + <value name="OR" value="0" /> + <value name="NAND" value="1" /> + </bitfield> + + <bitfield name="AUX2_SC_EN" high="2" low="2" /> + <bitfield name="AUX2_SC_MODE" high="3" low="3"> + <value name="OR" value="0" /> + <value name="NAND" value="1" /> + </bitfield> + + <bitfield name="AUX3_SC_EN" high="4" low="4" /> + <bitfield name="AUX3_SC_MODE" high="5" low="5"> + <value name="OR" value="0" /> + <value name="NAND" value="1" /> + </bitfield> + + + </reg32> + + <reg32 name="RADEON_DP_WRITE_MASK" offset="0x16cc" /> <reg32 name="RADEON_DEFAULT_OFFSET" offset="0x16e0" /> @@ -568,7 +794,9 @@ - <!-- + + <reg32 name="IDCT_RUNS" offset="0x1f80"> + <doc> IDCT ENGINE: It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag @@ -617,9 +845,8 @@ 0x0C0C: IDCT_AUTH Bits Usage 0-31 auth - --> + </doc> - <reg32 name="IDCT_RUNS" offset="0x1f80"> <bitfield name="IDCT_RUNS_3" high="7" low="0"/> <bitfield name="IDCT_RUNS_2" high="15" low="8"/> <bitfield name="IDCT_RUNS_1" high="23" low="16"/> |
From: <nou...@li...> - 2007-06-28 20:48:56
|
NouVeau CVS commit Author : pmandin Project : rules-ng Module : databases Dir : rules-ng/databases Added Files: nv_object_info.xml Log Message: Try to start object info |
From: <nou...@li...> - 2007-06-28 21:03:42
|
NouVeau CVS commit Author : pmandin Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nv_object_info.xml Log Message: All objects =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nv_object_info.xml,v retrieving revision 1.1 retrieving revision 1.2 diff -u -3 -r1.1 -r1.2 --- nv_object_info.xml 28 Jun 2007 20:48:48 -0000 1.1 +++ nv_object_info.xml 28 Jun 2007 21:03:44 -0000 1.2 @@ -5,13 +5,16 @@ <domain name="nv_obj_info" /> -<group name="nv_object_info"> - <doc>Default object infos, from nv04 to nv30.</doc> +<group name="nv03_object_info"> + <doc>nv03 object infos.</doc> <reg32 name="HANDLE" offset="0x00" /> <reg32 name="CONTEXT" offset="0x04"> - <bitfield name="CHANNEL" high="29" low="24" /> - <bitfield name="ENGINE" high="23" low="23" /> + <bitfield name="CHANNEL" high="28" low="24" /> + <bitfield name="ENGINE" high="23" low="23"> + <value name="software engine" value="0" /> + <value name="graphics engine" value="1" /> + </bitfield> <bitfield name="DMA_NOTIFIER_ID" high="15" low="0" /> </reg32> <reg32 name="DATA0" offset="0x08" /> @@ -20,4 +23,44 @@ <reg32 name="DATA3" offset="0x14" /> </group> +<group name="nv04_object_info"> + <doc>Object infos from nv04 to nv30.</doc> + + <reg32 name="HANDLE" offset="0x00" /> + <reg32 name="CONTEXT" offset="0x04"> + <bitfield name="CHANNEL" high="28" low="24" /> + <bitfield name="ENGINE" high="17" low="16"> + <value name="software engine" value="0" /> + <value name="graphics engine" value="1" /> + <value name="dvd engine" value="2" /> + <value name="unknown engine" value="3" /> + </bitfield> + <bitfield name="DMA_NOTIFIER_ID" high="15" low="0" /> + </reg32> + <reg32 name="DATA0" offset="0x08" /> + <reg32 name="DATA1" offset="0x0c" /> + <reg32 name="DATA2" offset="0x10" /> + <reg32 name="DATA3" offset="0x14" /> +</group> + +<group name="nv40_object_info"> + <doc>Object infos from nv40 to g80.</doc> + + <reg32 name="HANDLE" offset="0x00" /> + <reg32 name="CONTEXT" offset="0x04"> + <bitfield name="CHANNEL" high="27" low="23" /> + <bitfield name="ENGINE" high="21" low="20"> + <value name="software engine" value="0" /> + <value name="graphics engine" value="1" /> + <value name="dvd engine" value="2" /> + <value name="unknown engine" value="3" /> + </bitfield> + <bitfield name="DMA_NOTIFIER_ID" high="19" low="0" /> + </reg32> + <reg32 name="DATA0" offset="0x08" /> + <reg32 name="DATA1" offset="0x0c" /> + <reg32 name="DATA2" offset="0x10" /> + <reg32 name="DATA3" offset="0x14" /> +</group> + </database> |
From: <nou...@li...> - 2007-06-28 21:33:11
|
NouVeau CVS commit Author : pmandin Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nv_object_info.xml Log Message: More stuff =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nv_object_info.xml,v retrieving revision 1.3 retrieving revision 1.4 diff -u -3 -r1.3 -r1.4 --- nv_object_info.xml 28 Jun 2007 21:10:03 -0000 1.3 +++ nv_object_info.xml 28 Jun 2007 21:33:12 -0000 1.4 @@ -7,47 +7,84 @@ <group name="nv03_object_info"> <doc>nv03 object infos.</doc> - <reg32 name="HANDLE" offset="0x00" /> <reg32 name="CONTEXT" offset="0x04"> - <bitfield name="CHANNEL" high="28" low="24" /> + <bitfield name="DMA_NOTIFIER_ID" high="15" low="0" /> <bitfield name="ENGINE" high="23" low="23"> <value name="software engine" value="0" /> <value name="graphics engine" value="1" /> </bitfield> - <bitfield name="DMA_NOTIFIER_ID" high="15" low="0" /> + <bitfield name="CHANNEL" high="28" low="24" /> </reg32> </group> <group name="nv03_software_engine"> <doc>nv03 software engine data.</doc> - <reg32 name="DATA0" offset="0x00" /> - <reg32 name="DATA1" offset="0x04" /> - <reg32 name="DATA2" offset="0x08" /> - <reg32 name="DATA3" offset="0x0c" /> + <reg32 name="DATA0" offset="0x00"> + <bitfield name="CLASS" high="11" low="0" /> + <bitfield name="PAGE TABLE" high="12" low="12" /> + <bitfield name="PAGE ENTRY LINEAR" high="13" low="13" /> + <bitfield name="DMA ACCESS" high="15" low="14" /> + <bitfield name="DMA TARGET" high="17" low="16" /> + <bitfield name="DMA ADJUST" high="31" low="20" /> + </reg32> + <reg32 name="DATA1" offset="0x04"> + <bitfield name="DMA LIMIT" high="31" low="0" /> + </reg32> + <reg32 name="DATA2" offset="0x08"> + <bitfield name="DMA READ/WRITE" high="1" low="1" /> + <bitfield name="DMA PAGE ADDRESS" high="31" low="12" /> + </reg32> + <reg32 name="DATA3" offset="0x0c"> + <bitfield name="DMA READ/WRITE" high="1" low="1" /> + <bitfield name="DMA PAGE ADDRESS" high="31" low="12" /> + </reg32> </group> <group name="nv03_graphics_engine"> <doc>nv03 graphics engine data.</doc> - <reg32 name="DATA0" offset="0x00" /> - <reg32 name="DATA1" offset="0x04" /> - <reg32 name="DATA2" offset="0x08" /> + <reg32 name="DATA0" offset="0x00"> + <bitfield name="CLASS" high="11" low="0" /> + <bitfield name="CHROMA KEY" high="12" low="12" /> + <bitfield name="USER CLIP" high="13" low="13" /> + <bitfield name="SWIZZLE" high="14" low="14" /> + <bitfield name="PATCH" high="17" low="15" /> + <bitfield name="SYNCHRONIZED" high="18" low="18" /> + <bitfield name="BIG ENDIAN" high="19" low="19" /> + <bitfield name="DITHER" high="21" low="20" /> + <bitfield name="SINGLE STEP" high="23" low="23" /> + <bitfield name="PATCH VALID" high="24" low="24" /> + <bitfield name="SURFACE0" high="25" low="25" /> + <bitfield name="SURFACE1" high="26" low="26" /> + <bitfield name="PATTERN" high="27" low="27" /> + <bitfield name="ROP" high="28" low="28" /> + <bitfield name="BETA1" high="29" low="29" /> + <bitfield name="BETA4" high="30" low="30" /> + </reg32> + <reg32 name="DATA1" offset="0x04"> + <bitfield name="MONO FORMAT" high="7" low="0" /> + <bitfield name="COLOR FORMAT" high="15" low="8" /> + <bitfield name="DMA NOTIFIER" high="31" low="16" /> + </reg32> + <reg32 name="DATA2" offset="0x08"> + <bitfield name="DMA NOTIFIER" high="15" low="0" /> + <bitfield name="DMA NOTIFIER" high="31" low="16" /> + </reg32> <reg32 name="DATA3" offset="0x0c" /> </group> <group name="nv04_object_info"> <doc>Object infos from nv04 to nv30.</doc> - <reg32 name="HANDLE" offset="0x00" /> <reg32 name="CONTEXT" offset="0x04"> - <bitfield name="CHANNEL" high="28" low="24" /> + <bitfield name="DMA_NOTIFIER_ID" high="15" low="0" /> <bitfield name="ENGINE" high="17" low="16"> <value name="software engine" value="0" /> <value name="graphics engine" value="1" /> <value name="dvd engine" value="2" /> <value name="unknown engine" value="3" /> </bitfield> - <bitfield name="DMA_NOTIFIER_ID" high="15" low="0" /> + <bitfield name="CHANNEL" high="28" low="24" /> </reg32> </group> @@ -60,35 +97,58 @@ </group> <group name="nv40_object_info"> - <doc>Object infos from nv40 to g80.</doc> - + <doc>Object infos from nv40 to g80.</doc> <reg32 name="HANDLE" offset="0x00" /> <reg32 name="CONTEXT" offset="0x04"> - <bitfield name="CHANNEL" high="27" low="23" /> + <bitfield name="DMA_NOTIFIER_ID" high="19" low="0" /> <bitfield name="ENGINE" high="21" low="20"> <value name="software engine" value="0" /> <value name="graphics engine" value="1" /> <value name="dvd engine" value="2" /> <value name="unknown engine" value="3" /> </bitfield> - <bitfield name="DMA_NOTIFIER_ID" high="19" low="0" /> + <bitfield name="CHANNEL" high="27" low="23" /> </reg32> </group> <group name="nv40_software_engine"> <doc>nv40 software engine data.</doc> - <reg32 name="DATA0" offset="0x00" /> - <reg32 name="DATA1" offset="0x04" /> - <reg32 name="DATA2" offset="0x08" /> - <reg32 name="DATA3" offset="0x0c" /> + <reg32 name="DATA0" offset="0x00"> + <bitfield name="CLASS" high="15" low="0" /> + </reg32> + <reg32 name="DATA1" offset="0x04"> + <bitfield name="DMA LIMIT" high="31" low="0" /> + </reg32> + <reg32 name="DATA2" offset="0x08"> + <bitfield name="DMA READ/WRITE" high="1" low="1" /> + <bitfield name="DMA PAGE ADDRESS" high="31" low="12" /> + </reg32> + <reg32 name="DATA3" offset="0x0c"> + <bitfield name="DMA READ/WRITE" high="1" low="1" /> + <bitfield name="DMA PAGE ADDRESS" high="31" low="12" /> + </reg32> </group> <group name="nv40_graphics_engine"> <doc>nv40 graphics engine data.</doc> - <reg32 name="DATA0" offset="0x00" /> - <reg32 name="DATA1" offset="0x04" /> - <reg32 name="DATA2" offset="0x08" /> - <reg32 name="DATA3" offset="0x0c" /> + <reg32 name="DATA0" offset="0x00"> + <bitfield name="CLASS" high="15" low="0" /> + <bitfield name="USER CLIP" high="17" low="17" /> + <bitfield name="PATCH" high="21" low="19" /> + <bitfield name="PATCH VALID" high="25" low="25" /> + </reg32> + <reg32 name="DATA1" offset="0x04"> + <bitfield name="DMA NOTIFIER" high="19" low="0" /> + <bitfield name="BIG ENDIAN" high="24" low="24" /> + </reg32> + <reg32 name="DATA2" offset="0x08"> + <bitfield name="DMA NOTIFIER" high="19" low="0" /> + <bitfield name="BIG ENDIAN" high="24" low="24" /> + </reg32> + <reg32 name="DATA3" offset="0x0c"> + <bitfield name="DMA NOTIFIER" high="19" low="0" /> + <bitfield name="BIG ENDIAN" high="24" low="24" /> + </reg32> </group> <group name="nv40_dvd_engine"> @@ -99,4 +159,26 @@ <reg32 name="DATA3" offset="0x0c" /> </group> +<group name="nv50_graphics_engine"> + <doc>nv50 graphics engine data.</doc> + <reg32 name="DATA0" offset="0x00"> + <bitfield name="CLASS" high="15" low="0" /> + <bitfield name="USER CLIP" high="17" low="17" /> + <bitfield name="PATCH" high="21" low="19" /> + <bitfield name="PATCH VALID" high="25" low="25" /> + </reg32> + <reg32 name="DATA1" offset="0x04"> + <bitfield name="DMA NOTIFIER" high="15" low="0" /> + <bitfield name="DMA NOTIFIER" high="15" low="0" /> + </reg32> + <reg32 name="DATA2" offset="0x08"> + <bitfield name="DMA NOTIFIER" high="15" low="0" /> + <bitfield name="DMA NOTIFIER" high="15" low="0" /> + </reg32> + <reg32 name="DATA3" offset="0x0c"> + <bitfield name="DMA NOTIFIER" high="15" low="0" /> + <bitfield name="DMA NOTIFIER" high="15" low="0" /> + </reg32> +</group> + </database> |
From: <nou...@li...> - 2007-06-29 22:38:12
|
NouVeau CVS commit Author : pmandin Project : rules-ng Module : databases Dir : rules-ng/databases Added Files: nv_ramht.xml Removed Files: nv_object_info.xml Log Message: Rename nv_object_info.xml to nv_ramht.xml, and put there stuff from nouveau_reg.h and nouveau_object.c |
From: <nou...@li...> - 2007-07-02 13:27:05
|
NouVeau CVS commit Author : phillipezolt Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: r300_reg.xml Log Message: More R300 registers: Some GPIO stuff Some CP stuff =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/r300_reg.xml,v retrieving revision 1.5 retrieving revision 1.6 diff -u -3 -r1.5 -r1.6 --- r300_reg.xml 27 Jun 2007 18:58:08 -0000 1.5 +++ r300_reg.xml 2 Jul 2007 13:27:01 -0000 1.6 @@ -84,7 +84,17 @@ <bitfield name="RADEON_CRTC_EN" high="25" low="25" /> <bitfield name="RADEON_CRTC_DISP_REQ_EN_B" high="26" low="26" /> </reg32> - + <reg32 name="RADEON_CRTC_EXT_CNTL" offset="0x0054"> + <bitfield name="CRTC_VGA_XOVERSCAN" high="0" low="0" /> + <bitfield name="VGA_ATI_LINEAR" high="3" low="3" /> + <bitfield name="VGA_128KAP_PAGING" high="4" low="4" /> + <bitfield name="XCRT_CNT_EN" high="6" low="6" /> + <bitfield name="CRTC_HSYNC_DIS" high="8" low="8" /> + <bitfield name="CRTC_VSYNC_DIS" high="9" low="9" /> + <bitfield name="CRTC_DISPLAY_DIS" high="10" low="10" /> + <bitfield name="CRTC_SYNC_TRISTAT" high="11" low="11" /> + <bitfield name="CRTC_CRT_ON" high="15" low="15" /> + </reg32> <reg32 name="DAC_CNTL" offset="0x0058"> <bitfield name="DAC_RANGE" high="1" low="0" > @@ -107,6 +117,12 @@ </reg32> + <reg32 name="RADEON_CRTC_STATUS" offset="0x005C"> + <bitfield name="CRTC_VBLANK" high="0" low="0" /> + <bitfield name="CRTC_VBLANK_SAVE" high="1" low="1" > + <doc> This is for checking the vblank status. (Clear it, and then wait for it to go high. </doc> + </bitfield> + </reg32> <!-- from: drivers/video/aty/radeon_pm.c @@ -127,6 +143,10 @@ </reg32> + <reg32 name="RADEON_PALETTE_INDEX" offset="0x00B0"/> + <reg32 name="RADEON_PALETTE_DATA" offset="0x00B4"/> + <reg32 name="RADEON_PALETTE_30_DATA" offset="0x00B8"/> + <reg32 name="RADEON_RBBM_SOFT_RESET" offset="0x00F0"> <bitfield name="RADEON_SOFT_RESET_CP" high="0" low="0" /> @@ -212,6 +232,26 @@ </reg32> + <reg32 name="MEM_REFRESH_CNTL" offset="0x0178" > + <bitfield name="MEM_REFRESH_RATE" high="7" low="0"/> + <bitfield name="MEM_REFRESH_DIS" high="8" low="8"/> + <bitfield name="MEM_REFRESH_DYNAMIC_CKE" high="9" low="9"/> + <bitfield name="MEM_TRFC" high="15" low="12"/> + <bitfield name="MEM_CLKA0_ENABLE" high="16" low="16"/> + <bitfield name="MEM_CLKA0b_ENABLE" high="17" low="17"/> + <bitfield name="MEM_CLKA1_ENABLE" high="18" low="18"/> + <bitfield name="MEM_CLKA1b_ENABLE" high="19" low="19"/> + <bitfield name="MEM_CLKAFb_ENABLE" high="20" low="20"/> + <bitfield name="DLL_FB_SLCT_CKA" high="23" low="22"/> + + <bitfield name="MEM_CLKB0_ENABLE" high="24" low="24"/> + <bitfield name="MEM_CLKB0b_ENABLE" high="25" low="25"/> + <bitfield name="MEM_CLKB1_ENABLE" high="26" low="26"/> + <bitfield name="MEM_CLKB1b_ENABLE" high="27" low="27"/> + <bitfield name="MEM_CLKBFb_ENABLE" high="28" low="28"/> + <bitfield name="DLL_FB_SLCT_CKB" high="31" low="30"/> + </reg32> + <reg32 name="R300_MC_INIT_MISC_LAT_TIMER" offset="0x0180" > <bitfield name="MC_CPR_INIT_LAT" high="0" low="0"/> <bitfield name="MC_VF_INIT_LAT" high="4" low="4"/> @@ -222,6 +262,26 @@ <bitfield name="MC_SAME_PAGE_PRIO" high="24" low="24"/> <bitfield name="MC_GLOBW_INIT_LAT" high="28" low="28"/> </reg32> + <reg32 name="GPIOPAD_MASK" offset="0x0198" > + <doc> This has something to do with talking over the i2c bus + (And getting information about the attached monitors..?</doc> + </reg32> + + <reg32 name="GPIOPAD_A" offset="0x019C" > + <doc> This has something to do with talking over the i2c bus + (And getting information about the attached monitors..?</doc> + </reg32> + + + <reg32 name="GPIOPAD_EN" offset="0x01A0" > + <doc> This has something to do with talking over the i2c bus + (And getting information about the attached monitors..?</doc> + </reg32> + + <reg32 name="GPIOPAD_Y" offset="0x01A4" > + <doc> This has something to do with talking over the i2c bus + (And getting information about the attached monitors..?</doc> + </reg32> <reg32 name="RADEON_CRTC_H_TOTAL_DISP" offset="0x0200" > <bitfield name="RADEON_CRTC_H_TOTAL" high="9" low="0" /> @@ -255,6 +315,7 @@ <reg32 name="CRTC_OFFSET" offset="0x0224" /> + <reg32 name="CRTC_PITCH" offset="0x022C" /> <reg32 name="FP_GEN_CNTL" offset="0x0284" > <bitfield name="FP_FPON" high="0" low="0" /> @@ -434,6 +495,85 @@ <bitfield name="rb_wptr" high="22" low="0" /> </reg32> + <reg32 name="RADEON_CP_CSQ_CNTL" offset="0x0740" > + <bitfield name="RADEON_CSQ_CNT_PRIMARY_MASK" high="15" low="0" /> + <bitfield name="RADEON_CSQ" high="31" low="28" > + + <doc> I think that this indicates how the command + processor will recieve both direct and indirect + commands. </doc> + + <value name="PRIDIS_INDDIS" value="0"/> + <value name="PRIPIO_INDDIS" value="1"/> + <value name="PRIBM_INDDIS" value="2"/> + <value name="PRIPIO_INDBM" value="3"/> + <value name="PRIBM_INDBM" value="4"/> + <value name="PRIPIO_INDPIO" value="15"/> + </bitfield> + + + </reg32> + + <reg32 name="RADEON_CP_ME_CNTL" offset="0x07D0" > + <doc> From: http://www.handhelds.org/moin/moin.cgi/w100MMRegisters </doc> + <bitfield name="me_stat" high="15" low="0" > + <doc> Readback of internal CP register </doc> + </bitfield> + + <bitfield name="me_statmux" high="23" low="16" > + <doc> Specify internal CP register to read </doc> + </bitfield> + + <bitfield name="me_mode" high="30" low="30" > + <doc> Running Mode </doc> + <value name="SINGLE_STEP" value="0"/> + <value name="FREE_RUNNING" value="1"/> + </bitfield> + + <bitfield name="me_step" high="31" low="31" > + + <doc> When in single step mode, a low to high transition + on this bit will cause the next instruction to be + executed </doc> + + </bitfield> + </reg32> + + <reg32 name="RADEON_CP_ME_RAM_ADDR" offset="0x07D4" > + <doc> + This is the (auto-incrementing) addr of where the + firmware will be written. + </doc> + </reg32> + <reg32 name="RADEON_CP_ME_RAM_RADDR" offset="0x07D8" > + <doc> + This is the (auto-incrementing) addr of where the + firmware will be read from. + </doc> + </reg32> + <reg32 name="RADEON_CP_ME_RAM_DATAH" offset="0x07DC" > + <doc> + This is the high word of the firmware to be read/written. + </doc> + </reg32> + <reg32 name="RADEON_CP_ME_RAM_DATAL" offset="0x07E0" > + <doc> + This is the low word of the firmware to be read/written. + </doc> + </reg32> + + <reg32 name="RADEON_TV_RGB_CNTL" offset="0x0804"> + <bitfield name="RADEON_SWITCH_TO_BLUE" high="4" low="4" /> + <bitfield name="RADEON_RGB_DITHER_EN" high="5" low="5" /> + <bitfield name="RADEON_RGB_SRC_SEL" high="9" low="8" > + <value name="CRTC1" value="0" /> + <value name="RMX" value="1" /> + <value name="CRTC2" value="2" /> + </bitfield> + <bitfield name="RADEON_CONVERT_BY_PASS" high="10" low="10" /> + </reg32> + + <reg32 name="TV_DAC_CNTL" offset="0x088c"> <doc> 933 /* TV_DAC_CNTL constants */ @@ -476,6 +616,16 @@ </reg32> + <reg32 name="RADEON_CAP0_TRIG_CNTL" offset="0x0950" > + <bitfield name="UNKNOWN" high="4" low="0" > + <value name="DISABLE" value="0" /> + <value name="ENABLE" value="11" /> + </bitfield> + <doc> + (This is for video in..) + (0 looks like reset or disable 0x11 looks like enable) + </doc> + </reg32> <reg32 name="RADEON_SURFACE_CNTL" offset="0x0B00" > <bitfield name="RADEON_SURF_TRANSLATION_DIS" high="8" low="8" /> @@ -610,6 +760,16 @@ <reg32 name="RADEON_GUI_SCRATCH_REG3" offset="0x15ec" /> <reg32 name="RADEON_GUI_SCRATCH_REG4" offset="0x15f0" /> + + <reg32 name="RADEON_DST_LINE_START" offset="0x1600" > + <bitfield name="x" high="15" low="0" /> + <bitfield name="y" high="31" low="16" /> + </reg32> + + <reg32 name="RADEON_DST_LINE_END" offset="0x1604" > + <bitfield name="x" high="15" low="0" /> + <bitfield name="y" high="31" low="16" /> + </reg32> <!-- From: radeon_accelfuncs.c static void @@ -696,12 +856,12 @@ <bitfield name="DST_POLYLINE_NON_LAST" high="15" low="15"/> <bitfield name="DST_RASTER_STALL" high="16" low="16"/> <bitfield name="DST_POLY_EDGE" high="18" low="18"/> - </reg32> - - + <reg32 name="RADEON_DP_DATATYPE" offset="0x16c4" > + <bitfield name="RADEON_HOST_BIG_ENDIAN_EN" high="29" low="29" /> + </reg32> <reg32 name="RADEON__AUX_SC_CNTL" offset="0x1660" > <bitfield name="AUX1_SC_EN" high="0" low="0" /> @@ -785,6 +945,34 @@ </bitfield> </reg32> + <reg32 name="RADEON_RB3D_CNTL" offset="0x1C3C" > + <bitfield name="RADEON_ALPHA_BLEND_ENABLE" high="0" low="0"/> + <bitfield name="RADEON_PLANE_MASK_ENABLE" high="1" low="1"/> + <bitfield name="RADEON_DITHER_ENABLE" high="2" low="2"/> + <bitfield name="RADEON_ROUND_ENABLE" high="3" low="3"/> + <bitfield name="RADEON_SCALE_DITHER_ENABLE" high="4" low="4"/> + <bitfield name="RADEON_DITHER_INIT" high="5" low="5"/> + <bitfield name="RADEON_ROP_ENABLE" high="6" low="6"/> + <bitfield name="RADEON_STENCIL_ENABLE" high="7" low="7"/> + <bitfield name="RADEON_Z_ENABLE" high="8" low="8"/> + <bitfield name="RADEON_DEPTH_XZ_OFFEST_ENABLE" high="9" low="9"/> + <bitfield name="RADEON_COLOR_FORMAT" high="13" low="10"> + <value name="ARGB1555" value="3" /> + <value name="RGB565" value="4" /> + <value name="ARGB8888" value="6" /> + <value name="RGB332" value="7" /> + <value name="Y8" value="8" /> + <value name="RGB8" value="9" /> + <value name="YUV422_VYUY" value="11" /> + <value name="YUV422_YVYU" value="12" /> + <value name="aYUV444" value="14" /> + <value name="ARGB4444" value="15" /> + </bitfield> + <bitfield name="RADEON_CLRCMP_FLIP_ENABLE" high="14" low="14"/> + <bitfield name="RADEON_ZBLOCK16" high="15" low="15"/> + + </reg32> + <reg32 name="R300_SE_VPORT_XSCALE" offset="0x1d98" /> <reg32 name="R300_SE_VPORT_XOFFSET" offset="0x1d9c" /> <reg32 name="R300_SE_VPORT_YSCALE" offset="0x1da0" /> |
From: <nou...@li...> - 2007-07-05 16:32:01
|
NouVeau CVS commit Author : ppaalanen Project : rules-ng Module : databases Dir : rules-ng/databases Modified Files: nvregisters.xml Log Message: Some bitfields for NV03_PGRAPH_INTR. =================================================================== RCS file: /cvsroot/nouveau/rules-ng/databases/nvregisters.xml,v retrieving revision 1.17 retrieving revision 1.18 diff -u -3 -r1.17 -r1.18 --- nvregisters.xml 25 Jun 2007 22:27:57 -0000 1.17 +++ nvregisters.xml 5 Jul 2007 16:32:02 -0000 1.18 @@ -369,7 +369,13 @@ <bitfield name="PCIS_SPARE2" high="15" low="15" /> <bitfield name="PCIS_SPARE3" high="16" low="16" /> </reg32> - <reg32 name="NV03_PGRAPH_INTR" offset="0x00400100" /> + <reg32 name="NV03_PGRAPH_INTR" offset="0x00400100"> + <bitfield name="NOTIFY" high="0" low="0" /> + <bitfield name="MISSING_HW" high="4" low="4" /> + <bitfield name="CONTEXT_SWITCH" high="12" low="12" /> + <bitfield name="BUFFER_NOTIFY" high="16" low="16" /> + <bitfield name="ERROR" high="20" low="20" /> + </reg32> <reg32 name="NV03_PGRAPH_INTR_EN" offset="0x00400140" /> <reg32 name="NV03_PGRAPH_CTX_CONTROL" offset="0x00400190" /> <reg32 name="NV03_PGRAPH_CTX_USER" offset="0x00400194" /> |