New Verilog Plugin

2014-07-18
2014-07-18
  • Steve Kopman
    Steve Kopman
    2014-07-18

    I just recently uploaded a basic Verilog plugin for Notepad++. It currently has these features:

    Instantiate a module
    Insert registers/wires from a module
    Generate a test bench template
    Insert a clocked always block

    Currently only supports ANSI style module declarations.

    http://sourceforge.net/projects/nppverilog/

     
    Last edit: Steve Kopman 2014-07-18