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4bit adder inngspice using user defined model

Fahim
2012-09-24
2013-06-12
  • Fahim
    Fahim
    2012-09-24

    Hi, 
    I am trying to write four bit adder netlist.
    I have created the four bit adder code model with specification file having vector bound as .
    How should I write in the array format in net list.
    I am trying like this.

    *** analysis type ***
    .tran 1ps 4.5ns
    *
    *** input sources ***
    v1 100 0 DC PWL ( 0n 0.0 5n 0.0 5.5n 2.0 10n 0.0 10.5n 2.0 15n 2.0 15.5n 2.0 20n 0 20.5n 2.0 25n 2.0 25.5n 2.0 30n 2.0 30.5n 2.0
                    + 40n 0.0 50n 2.0 60n 0.0 70n 0.0 70.5n 2.0 80n 2.0 80.5 0.0 90 0.0 100 2.0)
    v2 200 0 DC PWL (0n 2.0 5n 2.0 10n 2.0 15n 2.0 15.5n 0.0 20n 0.0 25n 0.0 30n 0.0 30.5n 2.0 40n 2.0 40.5n 0.0 45n 2.0 50n 2.0 50.5n 0.0
                    + 60.0n 0.0 70n 0.0 80n 0.0 90n 0.0 95n 2.0 100n 0.0)
    v3 300 0 DC PWL (0n 0.0 5n 0.0 5.5n 0.0 10n 2.0 15n 2.0 15.5n 0.0 20n 0.0 20.5n 2.0 25n 2.0 25.5n 0.0 30n 2.0 35n 2.0 40n 0.0 50n 2.0
                    + 60n 0.0 65n 2.0 70n 0.0 75n 2.0 80n 0.0 90n 2.0 100n 0.0)
    v4 400 0 DC PWL (0n 2.0 5n 0.0 10n 2.0 15n 0.0 20n 2.0 25n 0.0 30n 2.0 40n 0.0 50n 2.0 60n 0.0 70n 2.0 80n 0.0 90n 2.0 100n 0.0)
    *** resistors to ground ***
    r1 100 0 1k
    r2 200 0 1k
    r3 300 0 1k
    r4 400 0 1k
    *
    *** adc_bridge blocks ***
    aconverter1 [100 200 300 400] [1 2 3 4] adc_bridge1
    .model adc_bridge1 adc_bridge ( in_low =0.3 in_high =0.7
    +                    rise_delay =1.0e-12 fall_delay =1.0e-12)
    *** d_ucm_adder blocks***
    add1 [1 2 3 4]  20  adder1
    .model adder1 my_adder(rise_delay = 1.0e-12 fall_delay = 1.0e-12)
    .end
    

    But thsi look like addition of 4 bit from four different source at a time also it is giving me error as

    Missing [, an array connection was expected.  Returning . . .Error on line 34 : add1  20 adder1
    Missing [, an array connection was expected

    Please let me know how can I use the vector bound properties in ngspice

    Regards,
    Fahim

     
  • Holger Vogt
    Holger Vogt
    2012-09-24

    What is the block diagram of your circuit (inputs, outputs) ?

    Holger

     
  • Fahim
    Fahim
    2012-09-25

    The block has two input A and B both are vector with vector bound .

    And output has Sum and Carry with Sum as Vector with vector bound   and Carry as single bit output.

    Rgards,
    Fahim

     
  • Holger Vogt
    Holger Vogt
    2012-09-25

    Fahim,

    but your example

    add1  20 adder1

    has a single 4 bit vector as input and a 1bit non vector as output. Does this correspond to your interface file description? It seems that your interface specification does require something different.

    To be able to tell you more I would need the complete ifs file listing.

    Holger

     
  • Fahim
    Fahim
    2012-09-25

    Please find the attached my ifs file

    NAME_TABLE:
    C_Function_Name: ucm_adder
    Spice_Model_Name: adder
    Description: " 4 bit adder. "
    PORT_TABLE:
    Port_Name:   A
    Description:   "input port A"
    Direction:  in
    Default_Type:  d
    Allowed_Types:  [d]
    Vector: yes
    Vector_Bounds: [4 4]
    Null_Allowed: no
    PORT_TABLE:
    Port_Name:   B
    Description:   "input port B"
    Direction:  in
    Default_Type:  d
    Allowed_Types:  [d]
    Vector: yes
    Vector_Bounds: [4 4]
    Null_Allowed: no
    PORT_TABLE:
    Port_Name:   CARRY
    Description:   "output port CARRY"
    Direction:  out
    Default_Type:  d
    Allowed_Types:  [d]
    Vector: no
    Vector_Bounds: -
    Null_Allowed: no
    PORT_TABLE:
    Port_Name:   SUM
    Description:   "output port SUM"
    Direction:  out
    Default_Type:  d
    Allowed_Types:  [d]
    Vector: yes
    Vector_Bounds: [4 4]
    Null_Allowed: no
    PARAMETER_TABLE:
    Parameter_Name:     rise_delay                  fall_delay
    Description:        "rise delay"                "fall delay"
    Data_Type:          real                        real
    Default_Value:      1.0e-9                      1.0e-9
    Limits:             [1e-12 -]                   [1e-12 -]
    Vector:              no                          no
    Vector_Bounds:       -                           -
    Null_Allowed:       yes                         yes
                                                                                                                                 5,1           Top
    
     
  • Fahim
    Fahim
    2012-09-25

    I have one question if I have to add 4 bit  then Do I need to creat 16 PWL signal for that.

    Also what would be the syntax instead of add1  20 adder1

    Regards,
    Fahim

     
  • Holger Vogt
    Holger Vogt
    2012-09-25

    Fahim,

    try this one:

    *             A              B      Carry       SUM
    add1 [1 2 3 4]  [5 6 7 8]  20   [9 10 11 12] adder1
    

    Holger

     
  • Holger Vogt
    Holger Vogt
    2012-09-25

    *        A          B    Carry       SUM
    add1 [1 2 3 4]  [5 6 7 8]  20   [9 10 11 12] adder1

    For an example of a more complex XSPICE input/output spec please see manual chapt. 12.4.18 State Machine.

    For an analog example of a 4bit full adder please see
    \ngspice\tests\general\fourbitadder.cir

    Holger

     
  • Fahim
    Fahim
    2012-09-25

    Thanks Holger!!!!!!!!!!!