with the current (experimental) version of ngspice you compiled me a lot of fascinating device+circuit simulations are possible. Thank you!
I am currently simulation an NPT-IGBT plus some small external circuitry. Since power devices feature a wide lightly-doped base region the grid for the device simulation (cider) has many nodes and the number of equations is therfore high, such that the simulations run not very fast.
My question is now: is there a chance, that more than one processor core is used for a coupled device+circuit simulation?
It seems that currently only one core is used (this tells me the task manager in windows).
basically there is a chance.
We have already OpenMP enabled for several MOS models. This allows evaluating several MOS transistor instances in parallel. Your example however has one transistor only, but a complex CIDER parameter evaluation. So we have to look for other places in the source code to be optimized.
I first step might be to do a little bit of profiling, to find out where the CPU time is spent during the analysis. I can do that if you provide me with some input file (you may send it to my sourceforge email account). I will publish the results here.
Then the difficult task: We have to find a volunteer to work on the code, which probably has not been touched for 20 years or so.
that sounds nice, thank you. I will do that.
What I thought of was more an improvement of the numerical core of the simulator. Maybe there are loops or functions, which could be executed in parallel.
I understand that this means a lot of work, hence it was only a question for feasibility.
Many thanks in advance.