#163 add support for LWP instructions

closed
nobody
None
1
2010-01-03
2010-01-01
nasm64developer
No

http://support.amd.com/us/Processor_TechDocs/43724.pdf

Ideally there'd be a LWP flag -- since there isn't one, I used AMD instead.

> LLWPCB reg16 [m: xop.m9.w0.l0.p0 12 /0] AMD
> LLWPCB reg32 [m: xop.m9.w0.l1.p0 12 /0] AMD,386
> LLWPCB reg64 [m: xop.m9.w1.l0.p0 12 /0] AMD,X64
>
> SLWPCB reg16 [m: xop.m9.w0.l0.p0 12 /1] AMD
> SLWPCB reg32 [m: xop.m9.w0.l1.p0 12 /1] AMD,386
> SLWPCB reg64 [m: xop.m9.w1.l0.p0 12 /1] AMD,X64
>
> LWPINS reg16,rm32,imm16 [vmi: xop.m10.w0.ndd.l0.p0 12 /0 iw] AMD,386
> LWPINS reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l1.p0 12 /0 id] AMD,386
> LWPINS reg64,rm32,imm32 [vmi: xop.m10.w1.ndd.l0.p0 12 /0 id] AMD,X64
>
> LWPVAL reg16,rm32,imm16 [vmi: xop.m10.w0.ndd.l0.p0 12 /1 iw] AMD,386
> LWPVAL reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l1.p0 12 /1 id] AMD,386
> LWPVAL reg64,rm32,imm32 [vmi: xop.m10.w1.ndd.l0.p0 12 /1 id] AMD,X64

A few testcases:

llwpcb ax
llwpcb cx
llwpcb dx
llwpcb bx
llwpcb sp
llwpcb bp
llwpcb si
llwpcb di
llwpcb r8w
llwpcb r9w
llwpcb r10w
llwpcb r11w
llwpcb r12w
llwpcb r13w
llwpcb r14w
llwpcb r15w
llwpcb eax
llwpcb ecx
llwpcb edx
llwpcb ebx
llwpcb esp
llwpcb ebp
llwpcb esi
llwpcb edi
llwpcb r8d
llwpcb r9d
llwpcb r10d
llwpcb r11d
llwpcb r12d
llwpcb r13d
llwpcb r14d
llwpcb r15d
llwpcb rax
llwpcb rcx
llwpcb rdx
llwpcb rbx
llwpcb rsp
llwpcb rbp
llwpcb rsi
llwpcb rdi
llwpcb r8
llwpcb r9
llwpcb r10
llwpcb r11
llwpcb r12
llwpcb r13
llwpcb r14
llwpcb r15

slwpcb r15
slwpcb r14
slwpcb r13
slwpcb r12
slwpcb r11
slwpcb r10
slwpcb r9
slwpcb r8
slwpcb rdi
slwpcb rsi
slwpcb rbp
slwpcb rsp
slwpcb rbx
slwpcb rdx
slwpcb rcx
slwpcb rax
slwpcb r15d
slwpcb r14d
slwpcb r13d
slwpcb r12d
slwpcb r11d
slwpcb r10d
slwpcb r9d
slwpcb r8d
slwpcb edi
slwpcb esi
slwpcb ebp
slwpcb esp
slwpcb ebx
slwpcb edx
slwpcb ecx
slwpcb eax
slwpcb r15w
slwpcb r14w
slwpcb r13w
slwpcb r12w
slwpcb r11w
slwpcb r10w
slwpcb r9w
slwpcb r8w
slwpcb di
slwpcb si
slwpcb bp
slwpcb sp
slwpcb bx
slwpcb dx
slwpcb cx
slwpcb ax

; repeat the following code for INS=... and IMM=...

%define2 INS ... ; lwpins,lwpval
%define2 IMM ... ; <empty>,byte,word,dword,qword,tword,oword,yword

; cases marked with ! will always fail
; cases marked with w will work for <empty> and word
; cases marked with d will work for <empty> and dword

; the F in the imm value will always warn

INS ax,bx,IMM 0xF1234 ;!
INS eax,bx,IMM 0xF12345678 ;!
INS rax,bx,IMM 0xF12345678 ;!

INS ax,ebx,IMM 0xF1234 ;w
INS eax,ebx,IMM 0xF12345678 ;d
INS rax,ebx,IMM 0xF12345678 ;d

INS ax,rbx,IMM 0xF1234 ;!
INS eax,rbx,IMM 0xF12345678 ;!
INS rax,rbx,IMM 0xF12345678 ;!

INS ax,[rax],IMM 0xF1234 ;w
INS eax,[rax],IMM 0xF12345678 ;d
INS rax,[rax],IMM 0xF12345678 ;d

INS ax,word [0],IMM 0xF1234 ;!
INS eax,word [0],IMM 0xF12345678 ;!
INS rax,word [0],IMM 0xF12345678 ;!

INS ax,dword [rax],IMM 0xF1234 ;w
INS eax,dword [rax],IMM 0xF12345678 ;d
INS rax,dword [rax],IMM 0xF12345678 ;d

INS ax,qword [0],IMM 0xF1234 ;!
INS eax,qword [0],IMM 0xF12345678 ;!
INS rax,qword [0],IMM 0xF12345678 ;!

Discussion

  • This has been implemented and checked into git, (http://repo.or.cz/w/nasm.git). It will be in the next version.

     
    • status: open --> closed