#30 User-defined code example: make self-contained

[Sjoerd Op 't Land]

I like to keep function definitions and user-defined code together, if possible. Would it be an improvement to the documentation (section 8.8) to change the example to:
---
def inc_comb(nextCount, count, n):
@always(count)
def logic():
# Python implementation (may be non-convertible)
nextCount.next = (count + 1) % n

# user-defined Verilog and VHDL implementations
inc_comb.verilog_code = """assign $nextCount = ($count + 1) % $n;"""
inc_comb.vhdl_code = """$nextCount <= ($count + 1) mod $n;"""
nextCount.driven = "wire"
count.read = True

return logic
---
Note that I added count.read and a Python implementation, to show that it is possible to have a Python function for simulation (possibly non-convertible). I admit that this is not a good example, because the modulo operation is actually convertible. Maybe we should pick another non-convertible (or not-automatically-convertible example)?