Commit [6596ff] master release/20120911 Maximize Restore History

Update for release

Peter A. Bigot Peter A. Bigot 2012-09-11

changed RELEASES.TXT
copied msp430-binutils-2.22-20120716.patch -> msp430-binutils-2.22-20120911.patch
copied msp430-gcc-4.7.0-20120716.patch -> msp430-gcc-4.7.0-20120911.patch
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msp430-binutils-2.22-20120716.patch to msp430-binutils-2.22-20120911.patch
--- a/msp430-binutils-2.22-20120716.patch
+++ b/msp430-binutils-2.22-20120911.patch
@@ -12,7 +12,7 @@
 This patch incorporates changes between:
   upstream/release/binutils-2.22 (3e07ad0fcb22e8fed15f5c86c8998ba5cec7ca0c)
 and
-  binutils-2_22/binutils-2.22 (64530e6fff5ac8b7bce6771c918f0d6ea87cb1cb)
+  binutils-2_22/binutils-2.22 (c35cfdccacef04f2618afe8ae5368c8cf8bd5ae0)
 
 To build, obtain the upstream release distribution from:
   ftp://ftp.gnu.org/pub/gnu/binutils/binutils-2.22.tar.bz2
@@ -21,7 +21,7 @@
 commands are in Bourne-shell syntax.)
 
   tar xjf binutils-2.22.tar.bz2
-  ( cd binutils-2.22 ; patch -p1 < ../msp430-binutils-2.22-20120716.patch )
+  ( cd binutils-2.22 ; patch -p1 < ../msp430-binutils-2.22-20120911.patch )
   mkdir -p BUILD/binutils
   cd BUILD/binutils
   ../../binutils-2.22/configure \
@@ -38,6 +38,8 @@
 https://sourceforge.net/tracker/?group_id=42303&atid=432701
 
 Log of relevant changes:
+3d91e75 [2012-09-11 09:15:14 -0500] Update DEV-PHASE for release
+d5323c6 [2012-09-10 10:45:37 -0500] SF 3554291 refine FRAM ISR fix
 9bae3ae [2012-07-16 14:32:05 -0500] Update DEV-PHASE for release
 1a0ef3d [2012-07-07 17:52:29 -0500] SF 3541237 truncated address in disassembled jmp
 0876ac8 [2012-07-02 06:28:15 -0500] Back-port upstream patch.
@@ -2235,12 +2237,12 @@
    msp430 specific relocation codes
  
 diff --git binutils-2.22.orig/bfd/version.h binutils-2.22/bfd/version.h
-index c6800ec..e971ea2 100644
+index c6800ec..2767280 100644
 --- binutils-2.22.orig/bfd/version.h
 +++ binutils-2.22/bfd/version.h
 @@ -1,4 +1,5 @@
  #define BFD_VERSION_DATE 20111121
-+#define BFD_MSPGCC_VERSION dev 20120716
++#define BFD_MSPGCC_VERSION dev 20120911
  #define BFD_VERSION @bfd_version@
  #define BFD_VERSION_STRING  @bfd_version_package@ @bfd_version_string@
  #define REPORT_BUGS_TO @report_bugs_to@
@@ -8916,10 +8918,10 @@
 +LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
 +LDEMUL_FINISH=gld${EMULATION_NAME}_finish
 diff --git binutils-2.22.orig/ld/scripttempl/elf32msp430.sc binutils-2.22/ld/scripttempl/elf32msp430.sc
-index cbffe48..e27e536 100644
+index cbffe48..c7bc137 100644
 --- binutils-2.22.orig/ld/scripttempl/elf32msp430.sc
 +++ binutils-2.22/ld/scripttempl/elf32msp430.sc
-@@ -1,206 +1,218 @@
+@@ -1,206 +1,255 @@
  #!/bin/sh
  
 -HEAP_SECTION_MSP430=" "
@@ -9257,6 +9259,43 @@
 +    *(.infod${RELOCATING+ .infod.*})
 +  } ${RELOCATING+ > infod}
 +
++  /* Values placed in the first 32 entries of a 64-entry interrupt vector
++   * table.  This exists because the FRAM chips place the BSL and JTAG
++   * passwords at specific offsets that technically fall within the
++   * interrupt table, but for which no MCU has a corresponding interrupt.
++   * See https://sourceforge.net/tracker/?func=detail&aid=3554291&group_id=42303&atid=432701 */
++  PROVIDE(__vte_0 = 0xffff);
++  PROVIDE(__vte_1 = 0xffff);
++  PROVIDE(__vte_2 = 0xffff);
++  PROVIDE(__vte_3 = 0xffff);
++  PROVIDE(__vte_4 = 0xffff);
++  PROVIDE(__vte_5 = 0xffff);
++  PROVIDE(__vte_6 = 0xffff);
++  PROVIDE(__vte_7 = 0xffff);
++  PROVIDE(__vte_8 = 0xffff);
++  PROVIDE(__vte_9 = 0xffff);
++  PROVIDE(__vte_10 = 0xffff);
++  PROVIDE(__vte_11 = 0xffff);
++  PROVIDE(__vte_12 = 0xffff);
++  PROVIDE(__vte_13 = 0xffff);
++  PROVIDE(__vte_14 = 0xffff);
++  PROVIDE(__vte_15 = 0xffff);
++  PROVIDE(__vte_16 = 0xffff);
++  PROVIDE(__vte_17 = 0xffff);
++  PROVIDE(__vte_18 = 0xffff);
++  PROVIDE(__vte_19 = 0xffff);
++  PROVIDE(__vte_20 = 0xffff);
++  PROVIDE(__vte_21 = 0xffff);
++  PROVIDE(__vte_22 = 0xffff);
++  PROVIDE(__vte_23 = 0xffff);
++  PROVIDE(__vte_24 = 0xffff);
++  PROVIDE(__vte_25 = 0xffff);
++  PROVIDE(__vte_26 = 0xffff);
++  PROVIDE(__vte_27 = 0xffff);
++  PROVIDE(__vte_28 = 0xffff);
++  PROVIDE(__vte_29 = 0xffff);
++  PROVIDE(__vte_30 = 0xffff);
++  PROVIDE(__vte_31 = 0xffff);
 +  .vectors ${RELOCATING-0} :
 +  {
 +    ${RELOCATING+ __vectors_start = .; }
@@ -9311,7 +9350,7 @@
  
    /* Stabs for profiling information*/
    .profiler 0 : { *(.profiler) }
-@@ -239,11 +251,13 @@ SECTIONS
+@@ -239,11 +288,13 @@ SECTIONS
    .debug_loc      0 : { *(.debug_loc) }
    .debug_macinfo  0 : { *(.debug_macinfo) }
  
msp430-gcc-4.7.0-20120716.patch to msp430-gcc-4.7.0-20120911.patch
--- a/msp430-gcc-4.7.0-20120716.patch
+++ b/msp430-gcc-4.7.0-20120911.patch
@@ -12,7 +12,7 @@
 This patch incorporates changes between:
   upstream/release/gcc-4.7.0 (3bd4897be46b07fb7c32a920c32713f313123a2a)
 and
-  gcc-4_7/gcc-4.7.0 (67db87a284ae0717a22505c4451ecdd9c5d59cfe)
+  gcc-4_7/gcc-4.7.0 (d4223f9ad984820cc1139621a9552d0285f4205e)
 
 To build, obtain the upstream release distribution from:
   ftp://ftp.gnu.org/pub/gnu/gcc/gcc-4.7.0/gcc-4.7.0.tar.bz2
@@ -21,7 +21,7 @@
 commands are in Bourne-shell syntax.)
 
   tar xjf gcc-4.7.0.tar.bz2
-  ( cd gcc-4.7.0 ; patch -p1 < ../msp430-gcc-4.7.0-20120716.patch )
+  ( cd gcc-4.7.0 ; patch -p1 < ../msp430-gcc-4.7.0-20120911.patch )
   mkdir -p BUILD/gcc
   cd BUILD/gcc
   ../../gcc-4.7.0/configure \
@@ -39,6 +39,13 @@
 https://sourceforge.net/tracker/?group_id=42303&atid=432701
 
 Log of relevant changes:
+47f3bbe [2012-09-11 09:14:43 -0500] Update DEV-PHASE for release
+51db7cb [2012-09-11 09:14:05 -0500] Update for release
+37e318e [2012-09-10 17:08:04 -0500] SF 3559978 broken volatile peephole optimization
+d74f307 [2012-09-10 15:36:30 -0500] SF 3562647 lack of memory model results in wrong data region
+e1a7bb5 [2012-09-10 12:37:00 -0500] SF 3562063 delay_cycles wrong when optimization disabled
+6acad2c [2012-09-10 11:10:27 -0500] SF 3554285 ICE: defining a far declared array w/o far
+cd8d8b5 [2012-09-10 07:59:24 -0500] SF 3554291 refine FRAM ISR fix
 58c8933 [2012-07-16 14:31:37 -0500] Update DEV-PHASE for release
 fb2facd [2012-07-16 14:30:41 -0500] Update for release
 b1dc3cd [2012-07-15 06:25:05 -0500] SF 3544338 large memory model induction variable optimization broken
@@ -839,11 +846,11 @@
      noconfigdirs="$noconfigdirs sim"
      ;;
 diff --git gcc-4.7.0.orig/gcc/DEV-PHASE gcc-4.7.0/gcc/DEV-PHASE
-index e69de29..4f95638 100644
+index e69de29..9d0a73c 100644
 --- gcc-4.7.0.orig/gcc/DEV-PHASE
 +++ gcc-4.7.0/gcc/DEV-PHASE
 @@ -0,0 +1 @@
-+mspgcc dev 20120716
++mspgcc dev 20120911
 diff --git gcc-4.7.0.orig/gcc/alias.c gcc-4.7.0/gcc/alias.c
 index e9d701f..e058b9f 100644
 --- gcc-4.7.0.orig/gcc/alias.c
@@ -1359,10 +1366,10 @@
 +
 diff --git gcc-4.7.0.orig/gcc/config/msp430/msp430-builtins.c gcc-4.7.0/gcc/config/msp430/msp430-builtins.c
 new file mode 100644
-index 0000000..06538bf
+index 0000000..e1b896d
 --- /dev/null
 +++ gcc-4.7.0/gcc/config/msp430/msp430-builtins.c
-@@ -0,0 +1,492 @@
+@@ -0,0 +1,483 @@
 +/* This work is partially financed by the European Commission under the
 +* Framework 6 Information Society Technologies Project
 +* "Wirelessly Accessible Sensor Populations (WASP)".
@@ -1749,7 +1756,6 @@
 +		if (itercnt0 > 0)
 +		  {
 +		    rtx loop_label = gen_label_rtx ();
-+		    rtx loop_test;
 +		    rtx iterreg1 = NULL_RTX;
 +
 +		    if (itercnt1 > 0)
@@ -1781,21 +1787,13 @@
 +
 +		    emit_label (loop_label);
 +		    emit_insn (gen_delay_cycles_decr (iterreg0));
-+		    loop_test =
-+		      gen_rtx_NE (itercnt_mode, iterreg0, const0_rtx);
 +		    gcc_assert (HImode == itercnt_mode);
-+		    emit_jump_insn (gen_cbranchhi4
-+				    (loop_test, iterreg0, const0_rtx,
-+				     loop_label));
++		    emit_jump_insn (gen_delay_cycles_jump (loop_label));
 +		    cycles -= itercnt0 * iter0_cycles;
 +		    if (iterreg1 != NULL_RTX)
 +		      {
 +			emit_insn (gen_delay_cycles_decr (iterreg1));
-+			loop_test =
-+			  gen_rtx_NE (itercnt_mode, iterreg1, const0_rtx);
-+			emit_jump_insn (gen_cbranchhi4
-+					(loop_test, iterreg1, const0_rtx,
-+					 loop_label));
++			emit_jump_insn (gen_delay_cycles_jump (loop_label));
 +			cycles -=
 +			  itercnt1 * iter1_cycles + iter_overhead_cycles;
 +		      }
@@ -3320,10 +3318,10 @@
 +     extern int msp430_cfa_frame_base_offset (const_tree decl);
 diff --git gcc-4.7.0.orig/gcc/config/msp430/msp430.c gcc-4.7.0/gcc/config/msp430/msp430.c
 new file mode 100644
-index 0000000..c83cb5a
+index 0000000..336630b
 --- /dev/null
 +++ gcc-4.7.0/gcc/config/msp430/msp430.c
-@@ -0,0 +1,4173 @@
+@@ -0,0 +1,4174 @@
 +/* TODO
 + * cost speed attribute
 + */
@@ -4055,7 +4053,9 @@
 +	      int dist = msp430_jump_dist (if_loc, insn);
 +	      bool in_range = MSP430_JUMP_IN_RANGE (dist);
 +
-+	      gcc_assert (XEXP (cmp, 0) == cc0_rtx);
++	      gcc_assert (XEXP (cmp, 0) == cc0_rtx
++			  || (UNSPEC_VOLATILE == GET_CODE (XEXP (cmp, 0))
++			      && XVECEXP (XEXP (cmp, 0), 0, 0) == cc0_rtx));
 +	      gcc_assert (XEXP (cmp, 1) == const0_rtx);
 +	      gcc_assert (else_loc == pc_rtx);
 +	      switch (GET_CODE (cmp))
@@ -6296,7 +6296,7 @@
 +      && FUNCTION_DECL == TREE_CODE (decl)
 +      && NULL_TREE != lookup_attribute (S_interrupt, DECL_ATTRIBUTES (decl)))
 +    return MSP430_SECTION_REGION_NEAR;
-+  if (MSP430_MEMORY_MODEL_NONE == msp430_memory_model)
++  if (! TARGET_CPUX)
 +    return MSP430_SECTION_REGION_DEFAULT;
 +  if (VAR_OR_FUNCTION_DECL_P (decl))
 +    {
@@ -7028,12 +7028,11 @@
 +  tree d20a = lookup_attribute (S_d20, TYPE_ATTRIBUTES (type1));
 +  tree d20b = lookup_attribute (S_d20, TYPE_ATTRIBUTES (type2));
 +
-+  /* Failure of these assertions is probably a mistake in user code
-+   * which should be diagnosed.  Until I can find a case that causes
-+   * failure, so I can figure out what it should do, these will cause
-+   * ICEs. */
-+  gcc_assert ((NULL_TREE == d16a) == (NULL_TREE == d16b));
-+  gcc_assert ((NULL_TREE == d20a) == (NULL_TREE == d20b));
++  /* Failure of these assertions is a mistake in user code which
++   * should be diagnosed. */
++  if (((NULL_TREE == d16a) != (NULL_TREE == d16b))
++      || ((NULL_TREE == d20a) != (NULL_TREE == d20b)))
++    error (_("merged types have inconsistent d16/d20 attributes"));
 +  return merge_type_attributes (type1, type2);
 +}
 +#undef TARGET_MERGE_TYPE_ATTRIBUTES
@@ -7499,7 +7498,7 @@
 +#include "gt-msp430.h"
 diff --git gcc-4.7.0.orig/gcc/config/msp430/msp430.h gcc-4.7.0/gcc/config/msp430/msp430.h
 new file mode 100644
-index 0000000..50308af
+index 0000000..b740c28
 --- /dev/null
 +++ gcc-4.7.0/gcc/config/msp430/msp430.h
 @@ -0,0 +1,776 @@
@@ -7546,7 +7545,7 @@
 + */
 +
 +/** Update this on each release */
-+#define MSP430_MSPGCC_VERSION 20120716
++#define MSP430_MSPGCC_VERSION 20120911
 +
 +#include "config/msp430/msp430-opts.h"
 +
@@ -8281,10 +8280,10 @@
 +#endif /* GCC_MSP430_H */
 diff --git gcc-4.7.0.orig/gcc/config/msp430/msp430.md gcc-4.7.0/gcc/config/msp430/msp430.md
 new file mode 100644
-index 0000000..bffca7a
+index 0000000..1d13c1b
 --- /dev/null
 +++ gcc-4.7.0/gcc/config/msp430/msp430.md
-@@ -0,0 +1,1648 @@
+@@ -0,0 +1,1660 @@
 +;; -*- Mode: Scheme -*-
 +;;   Machine description for GNU compiler,
 +;;   for Texas Instruments msp430 MCUs
@@ -8781,6 +8780,18 @@
 +  [(set_attr "cc" "VNZC")
 +   (set_attr "instr_format" "fmt1")])
 +
++; delay_cycles_jump(loophead)
++(define_insn "delay_cycles_jump"
++  [(set (pc)
++	(if_then_else
++	 (ne (unspec_volatile [(cc0)] UNSPECV_DELAY_CYCLES) (const_int 0))
++	 (label_ref (match_operand 0 "" ""))
++	 (pc)))]
++  ""
++  "jne\t%0"
++  [(set_attr "cc" "none")
++   (set_attr "instr_format" "condjmp")])
++
 +; get_watchdog_clear_value(retloc)
 +(define_insn "get_watchdog_clear_value"
 +  [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
@@ -10108,7 +10119,7 @@
 +-mdata-region=REGION  Override default placement of data when -md20 in effect
 diff --git gcc-4.7.0.orig/gcc/config/msp430/peephole.md gcc-4.7.0/gcc/config/msp430/peephole.md
 new file mode 100644
-index 0000000..2a20e38
+index 0000000..c696ff2
 --- /dev/null
 +++ gcc-4.7.0/gcc/config/msp430/peephole.md
 @@ -0,0 +1,254 @@
@@ -10193,21 +10204,21 @@
 +  "")
 +
 +;; Assignment to volatile memory through a cast constant pointer
-+;; mov #c1, r0; mov &m3, r2; op4 g5, r2; mov r2, @r0 => op g4, &c1 [r0 dead, r2 dead]
-+; see testsuite vwa4.c
++;; mov #c1, r0; mov @r0, r2; op3 g4, r2; mov r2, @r0 => op3 g4, &c1 [r0 dead, r2 dead]
++; see testsuite vwa4.c, sf3559978.c
 +(define_peephole2
 +  [(set (match_operand 0 "pmode_register_operand" "") 
 +	(match_operand 1 "immediate_operand" ""))
 +   (set (match_operand:INTRegModes 2 "register_operand" "") 
-+	(match_operand:<MODE> 3 "nonimmediate_operand" ""))
++	(mem:<MODE> (match_dup 0)))
 +   (set (match_dup 2) 
-+	(match_operator:<MODE> 4 "msp430_rmw_operator"
++	(match_operator:<MODE> 3 "msp430_rmw_operator"
 +			       [(match_dup 2)
-+				(match_operand:<MODE> 5 "general_operand" "")]))
++				(match_operand:<MODE> 4 "general_operand" "")]))
 +   (set (mem:<MODE> (match_dup 0)) (match_dup 2))]
 +  "peep2_reg_dead_p (4, operands[0]) && peep2_reg_dead_p (4, operands[2])"
 +  [(set (mem:<MODE> (match_dup 1))
-+	(match_op_dup 4 [(mem:<MODE> (match_dup 1)) (match_dup 5)]))]
++	(match_op_dup 3 [(mem:<MODE> (match_dup 1)) (match_dup 4)]))]
 +  "")
 +
 +
@@ -14067,6 +14078,39 @@
 +#pragma vector=11
 +__attribute__((interrupt))
 +void isr11 () { }  /* { dg-error "interrupt vector offset 11 must be even and non-negative" } */
+diff --git gcc-4.7.0.orig/gcc/testsuite/gcc.target/msp430/sf3559978.c gcc-4.7.0/gcc/testsuite/gcc.target/msp430/sf3559978.c
+new file mode 100644
+index 0000000..8801ddc
+--- /dev/null
++++ gcc-4.7.0/gcc/testsuite/gcc.target/msp430/sf3559978.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "-Os" } */
++
++static volatile struct sTransmitBuffer {
++  volatile char * head;
++  volatile char * tail;
++  char buffer[256];
++  unsigned int wake_when_available;
++} txBuffer;
++
++void initialize ()
++{
++  txBuffer.tail = txBuffer.buffer; /* { dg-final { scan-assembler "mov\t#txBuffer\\+2, r15\n\tmov\tr15, r14\n\tadd\t#2, r14\n\tmov\tr14, @r15\n" } } */
++}
++
+diff --git gcc-4.7.0.orig/gcc/testsuite/gcc.target/msp430/sf3562063.c gcc-4.7.0/gcc/testsuite/gcc.target/msp430/sf3562063.c
+new file mode 100644
+index 0000000..6d2b9ab
+--- /dev/null
++++ gcc-4.7.0/gcc/testsuite/gcc.target/msp430/sf3562063.c
+@@ -0,0 +1,6 @@
++/* { dg-do compile } */
++void foo ()
++{
++  /* { dg-final { scan-assembler "\tmov\t#3, r15\n.L2:\n\tdec\tr15\n\tjne\t.L2\n" } } */
++  __delay_cycles (11);
++}
 diff --git gcc-4.7.0.orig/gcc/testsuite/gcc.target/msp430/target_isr20.c gcc-4.7.0/gcc/testsuite/gcc.target/msp430/target_isr20.c
 new file mode 100644
 index 0000000..12c02b1
@@ -15474,10 +15518,10 @@
 +#endif
 diff --git gcc-4.7.0.orig/libgcc/config/msp430/crt0ivtbl.S gcc-4.7.0/libgcc/config/msp430/crt0ivtbl.S
 new file mode 100644
-index 0000000..68dff23
+index 0000000..1feb18a
 --- /dev/null
 +++ gcc-4.7.0/libgcc/config/msp430/crt0ivtbl.S
-@@ -0,0 +1,146 @@
+@@ -0,0 +1,156 @@
 +/*  -*- Mode: Asm -*-  */
 +
 +#if __MSP430X__ - 0	
@@ -15492,6 +15536,11 @@
 + *	User may not define its interrupt service routines!
 + ***************************************************************/
 +	
++.macro  INITIALIZE_VTE_SLOT sn
++        .global   __vte_\sn
++	.word	__vte_\sn
++.endm
++
 +.macro  INITIALIZE_ISR_SLOT sn
 +        .weak   __isr_\sn
 +        .equ    __isr_\sn, __br_unexpected_
@@ -15512,6 +15561,7 @@
 +
 +	.global	_unexpected_
 +	.global	_reset_vector__
++
 +        .section .vectors, "ax", @progbits
 +	
 +DEFINE_IVTABLE INTERRUPT_VECTOR_COUNT
@@ -15552,45 +15602,49 @@
 +#endif /* 16 < INTERRUPT_VECTOR_COUNT */
 +#else /* 32 >= INTERRUPT_VECTOR_COUNT */
 +/* SF 3540953 fram applications overwrite bsl/jtag passwords
-+ * 
-+ * No MSP430 chip has more than 25 valid interrupts, and they are assigned from
-+ * the top down.  The FRAM chips use lower words in the interrupt vector to
-+ * hold BSL and JTAG passwords, and having real addresses in those locations
-+ * has been shown to result in problems accessing BSL and JTAG.  Leave the low
-+ * 32 words erased; this matches as-delivered MSP430FR5739 content for those
-+ * addresses. */
-+	.word	0xffff		; 0
-+	.word	0xffff		; 1
-+	.word	0xffff		; 2
-+	.word	0xffff		; 3
-+	.word	0xffff		; 4
-+	.word	0xffff		; 5
-+	.word	0xffff		; 6
-+	.word	0xffff		; 7
-+	.word	0xffff		; 8
-+	.word	0xffff		; 9
-+	.word	0xffff		; 10
-+	.word	0xffff		; 11
-+	.word	0xffff		; 12
-+	.word	0xffff		; 13
-+	.word	0xffff		; 14
-+	.word	0xffff		; 15
-+	.word	0xffff		; 16
-+	.word	0xffff		; 17
-+	.word	0xffff		; 18
-+	.word	0xffff		; 19
-+	.word	0xffff		; 20
-+	.word	0xffff		; 21
-+	.word	0xffff		; 22
-+	.word	0xffff		; 23
-+	.word	0xffff		; 24
-+	.word	0xffff		; 25
-+	.word	0xffff		; 26
-+	.word	0xffff		; 27
-+	.word	0xffff		; 28
-+	.word	0xffff		; 29
-+	.word	0xffff		; 30
-+	.word	0xffff		; 31
++ * SF 3554291 refine FRAM ISR fix
++ *
++ * No current MSP430 chip has more than 25 valid interrupts, and they
++ * are assigned from the top down.  The FRAM chips use lower words in
++ * the interrupt vector to hold BSL and JTAG passwords, and having
++ * real addresses in those locations has been shown to result in
++ * problems accessing BSL and JTAG.  For these MCUs, allow the lower
++ * 32 vector table entry values to be independently assigned.  The
++ * default value is 0xFFFF, corresponding to the erased state, and
++ * is provided in the primary linker script in binutils when no
++ * entry-specific value is provided. */
++	INITIALIZE_VTE_SLOT 0
++	INITIALIZE_VTE_SLOT 1
++	INITIALIZE_VTE_SLOT 2
++	INITIALIZE_VTE_SLOT 3
++	INITIALIZE_VTE_SLOT 4
++	INITIALIZE_VTE_SLOT 5
++	INITIALIZE_VTE_SLOT 6
++	INITIALIZE_VTE_SLOT 7
++	INITIALIZE_VTE_SLOT 8
++	INITIALIZE_VTE_SLOT 9
++	INITIALIZE_VTE_SLOT 10
++	INITIALIZE_VTE_SLOT 11
++	INITIALIZE_VTE_SLOT 12
++	INITIALIZE_VTE_SLOT 13
++	INITIALIZE_VTE_SLOT 14
++	INITIALIZE_VTE_SLOT 15
++	INITIALIZE_VTE_SLOT 16
++	INITIALIZE_VTE_SLOT 17
++	INITIALIZE_VTE_SLOT 18
++	INITIALIZE_VTE_SLOT 19
++	INITIALIZE_VTE_SLOT 20
++	INITIALIZE_VTE_SLOT 21
++	INITIALIZE_VTE_SLOT 22
++	INITIALIZE_VTE_SLOT 23
++	INITIALIZE_VTE_SLOT 24
++	INITIALIZE_VTE_SLOT 25
++	INITIALIZE_VTE_SLOT 26
++	INITIALIZE_VTE_SLOT 27
++	INITIALIZE_VTE_SLOT 28
++	INITIALIZE_VTE_SLOT 29
++	INITIALIZE_VTE_SLOT 30
++	INITIALIZE_VTE_SLOT 31
 +	INITIALIZE_ISR_SLOT 32
 +	INITIALIZE_ISR_SLOT 33
 +	INITIALIZE_ISR_SLOT 34