[MinGW-cvs] [git push msys2-runtime]Repository: msys2-runtime branch, cygwin, updated. e7992abe1fe6

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- Log -----------------------------------------------------------------
https://sf.net/p/mingw/msys2-runtime/ci/e7992abe1fe6bcb7b9a6b3103b46adc1a4c06084/

commit e7992abe1fe6bcb7b9a6b3103b46adc1a4c06084
Author: Nick Clifton <ni...@re...>
Date:   Wed Mar 20 16:56:34 2013 +0000

    	PR gas/15082
    	* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
    	from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
    	tic6x_operand_xregpair operand coding type.
    	Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
    	opcode field, usu ORXREGD1324 for the src2 operand and remove the
    	TIC6X_FLAG_NO_CROSS.
    
    	* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
    	cross-path.
    	* gas/tic6x/insns-bad-1.l: Update expected output.
    	* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
    	cross-path.
    	* gas/tic6x/insns-c674x.d: Update expected output.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 69d0859..cc7ef5f 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,5 +1,15 @@
 2013-03-20  Alexis Deruelle  <ale...@gm...>
 
+	PR gas/15082
+	* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
+	from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
+	tic6x_operand_xregpair operand coding type.
+	Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
+	opcode field, usu ORXREGD1324 for the src2 operand and remove the
+	TIC6X_FLAG_NO_CROSS.
+
+2013-03-20  Alexis Deruelle  <ale...@gm...>
+
 	PR gas/15095
 	* tic6x.h (enum tic6x_coding_method): Add
 	tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h
index abebd3c..e9cfab9 100644
--- a/include/opcode/tic6x-opcode-table.h
+++ b/include/opcode/tic6x-opcode-table.h
@@ -75,7 +75,7 @@
 #define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
 #define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 }
 #define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 }
-#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
+#define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 }
 #define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 }
 #define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 }
 #define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 }
@@ -1154,11 +1154,11 @@ INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0,
       ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0),
 	   ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
-INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX2(FIX(op, 0x0e), FIX(x, 0)),
-     OP3(ORREGD1234, ORREGD1324, OWREGD910),
-     ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1),
-	  ENC(dst, reg, 2)))
+INSN(mpydp, m, mpy, mpydp, C67X, 0,
+     FIX1(FIX(op, 0x0e)),
+     OP3(ORREGD1234, ORXREGD1324, OWREGD910),
+     ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0),
+           ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
 INSN(mpyh, m, mpy, 1616_m, C62X, 0,
      FIX1(FIX(op, 0x01)),
@@ -2520,7 +2520,7 @@ INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X,
 #undef OWDREGD5
 #undef ORREGD12
 #undef ORXREGD12
-#undef ORREGD1234
+#undef ORXREGD1234
 #undef ORREGD1324
 #undef OWREGD910
 #undef ORCREG1

https://sf.net/p/mingw/msys2-runtime/ci/88d21df654b3e9cac9363b72c838eb5209b3088e/

commit 88d21df654b3e9cac9363b72c838eb5209b3088e
Author: Nick Clifton <ni...@re...>
Date:   Wed Mar 20 16:36:34 2013 +0000

    * include/opcode/tic6x.h: add tic6x_coding_dreg_(msb|lsb) field coding type in
    order to encode separately the msb and lsb of a register pair ; this will be
    needed to encode the opcodes the same
    way as Ti assembler does.
    
    * gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb)  field coding types
    and use it to encode register pair numbers when required.
    
    * opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
    in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
    discarding bit 0, to follow what Ti SDK does in that case as any value in the
    src1 field yields the same output with SDK disassembler.
    
    * include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
    rcpdp and rsqrdp opcodes to use the new field coding types.
    
    * gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
    : add test case for the newly generated opcode but keep the old ones as they
    seem legit as per Ti disassembler output.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index a46900a..69d0859 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,13 @@
+2013-03-20  Alexis Deruelle  <ale...@gm...>
+
+	PR gas/15095
+	* tic6x.h (enum tic6x_coding_method): Add
+	tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
+	separately the msb and lsb of a register pair.  This is needed to
+	encode the opcodes in the same way as TI assembler does.
+	* tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
+	and rsqrdp opcodes to use the new field coding types.
+
 2013-03-11  Kyrylo Tkachov  <kyr...@ar...>
 
 	* arm.h (CRC_EXT_ARMV8): New constant.
diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h
index 45e26fb..abebd3c 100644
--- a/include/opcode/tic6x-opcode-table.h
+++ b/include/opcode/tic6x-opcode-table.h
@@ -1,6 +1,5 @@
 /* TI C6X opcode table.
-   Copyright 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright 2010-2013 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -129,9 +128,10 @@ INSN(abs2, l, unary, 1cycle, C64X, 0,
 	  ENC(dst, reg, 1)))
 
 INSN(absdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x2c), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x2c), FIX(x, 0)),
      OP2(ORREGD1, OWREGD12),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
 
 INSN(abssp, s, unary, 1cycle, C67X, 0,
      FIX1(FIX(op, 0)),
@@ -916,19 +916,22 @@ INSN(dpackx2, l, 1_or_2_src_noncond, 1cycle, C64XP, 0,
 	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
 INSN(dpint, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x8), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x8), FIX(x, 0)),
      OP2(ORREGD1, OWREG4),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
 
 INSN(dpsp, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x9), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x9), FIX(x, 0)),
      OP2(ORREGD1, OWREG4),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
 
 INSN(dptrunc, l, 1_or_2_src, 4cycle, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x1), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x1), FIX(x, 0)),
      OP2(ORREGD1, OWREG4),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
 
 INSN(ext, s, field, 1cycle, C62X, TIC6X_FLAG_NO_CROSS,
      FIX1(FIX(op, 0x1)),
@@ -1617,9 +1620,10 @@ INSN(packl4, l, 1_or_2_src, 1cycle, C64X, 0,
 	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
 INSN(rcpdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x2d), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x2d), FIX(x, 0)),
      OP2(ORREGD1, OWREGD12),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
 
 INSN(rcpsp, s, 1_or_2_src, 1cycle, C67X, 0,
      FIX2(FIX(op, 0x3d), FIX(src1, 0)),
@@ -1677,9 +1681,10 @@ INSN(rpack2, s, ext_1_or_2_src_noncond, 1cycle, C64XP, 0,
 	  ENC(src2, reg, 1), ENC(dst, reg, 2)))
 
 INSN(rsqrdp, s, 1_or_2_src, 2cycle_dp, C67X, TIC6X_FLAG_NO_CROSS,
-     FIX3(FIX(op, 0x2e), FIX(x, 0), FIX(src1, 0)),
+     FIX2(FIX(op, 0x2e), FIX(x, 0)),
      OP2(ORREGD1, OWREGD12),
-     ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
+     ENC4(ENC(s, fu, 0), ENC(src2, regpair_msb, 0), ENC(src1, regpair_lsb, 0),
+	  ENC(dst, reg, 1)))
 
 INSN(rsqrsp, s, 1_or_2_src, 1cycle, C67X, 0,
      FIX2(FIX(op, 0x3e), FIX(src1, 0)),
diff --git a/include/opcode/tic6x.h b/include/opcode/tic6x.h
index 2a7a246..168f660 100644
--- a/include/opcode/tic6x.h
+++ b/include/opcode/tic6x.h
@@ -1,6 +1,5 @@
 /* TI C6X opcode information.
-   Copyright 2010, 2011
-   Free Software Foundation, Inc.
+   Copyright 2010-2013 Free Software Foundation, Inc.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -380,6 +379,12 @@ typedef enum
        the field.  When applied to a memory reference, encode the base
        register.  */
     tic6x_coding_reg,
+    /* Encode the register-pair's lsb (even register) for instructions
+       that use src1 as port for loading lsb of double-precision
+       operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp).  */
+    tic6x_coding_regpair_lsb,
+    /* Encode the register-pair's msb (odd register), see above.  */ 
+    tic6x_coding_regpair_msb,
     /* Store 0 for register B14, 1 for register B15.  When applied to
        a memory reference, encode the base register.  */
     tic6x_coding_areg,

https://sf.net/p/mingw/msys2-runtime/ci/3b1b023c9d65e0bca9816281e77fd7fcae85d1cd/

commit 3b1b023c9d65e0bca9816281e77fd7fcae85d1cd
Author: Christopher Faylor <me....@cg...>
Date:   Tue Mar 19 16:41:42 2013 +0000

    test checkin

diff --git a/winsup/cygwin/release/1.7.18 b/winsup/cygwin/release/1.7.18
index 977ae18..148d441 100644
--- a/winsup/cygwin/release/1.7.18
+++ b/winsup/cygwin/release/1.7.18
@@ -17,7 +17,7 @@ What's new:
 
 - Changes in cygwin1.dll and gdb-7.5.50-2 now allow gdb to recognize
   Cygwin-specific signals like "SIGTERM" as well as Windows signals like
-  "SIGSEGV".
+  "SIGSEGV".  This feature is still experimental.
 
 Bug fixes:
 ----------

-----------------------------------------------------------------------

Summary of changes:
 include/opcode/ChangeLog            |   20 +++++++++++++++
 include/opcode/tic6x-opcode-table.h |   47 +++++++++++++++++++---------------
 include/opcode/tic6x.h              |    9 +++++-
 winsup/cygwin/release/1.7.18        |    2 +-
 4 files changed, 54 insertions(+), 24 deletions(-)


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