[Lse-tech] PATCH: configurable pools for the pooling MQ scheduler

[Erich F. <ef...@es...>]

Hi,

the appended patch is for the pooling MQ scheduler. It allows a slightly
more flexible configuration of CPU pools by using the kernel argument
"pools=cpus1,cpus2,..."
with cpusX specifying the number of CPUs in each pool. This can be used
to play around with fake-nodes. Also useful if the nodes are not
populated
equally with CPUs.

Additionally when CONFIG_IA64_DIG is defined (i.e. DIG64 compliant IA64
hardware) and the option "pools=" is omitted from the kernel command
line,
the pools are configured by trying to deduct the node numbers from the
hardware CPU IDs. This means automatic configuration of the pools for
the NEC AzusA, on the Intel BigSur and LION it configures (correctly)
only
one node. If it doesn't work or your platform either use "pools=" or
adapt
the bld_node_number() function.

The hardware CPU IDs are sorted before booting the CPUs, just in case
the
firmware doesn't deliver the IDs in ascending node order. This is needed
in
order to keep the cpu_logical_map() an identity mapping. I also added
checks
to the cpu_online_map to be a bit prepared for the hot-plug patches.

Comments, improvements, etc. are welcome. An inclusion in the mq-pool
patch would also be nice.

Thanks,
Erich