Diff of /kernel/linux-03.20.00.13/arch/arm/mach-davinci/cp_intc.c [05165e] .. [ee86d7] Maximize Restore

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--- a/kernel/linux-03.20.00.13/arch/arm/mach-davinci/cp_intc.c
+++ b/kernel/linux-03.20.00.13/arch/arm/mach-davinci/cp_intc.c
@@ -102,9 +102,19 @@
 	return 0;
 }
 
-void default_fiq_handler(void)
-{
-  cp_intc_ack_irq(cp_intc_get_hpir(0));
+/*
+ * Default fiq handler. Do nothing.
+ */
+static void default_fiq_handler(void)
+{
+	cp_intc_ack_irq(cp_intc_get_hpir(0));
+}
+
+static int cp_intc_fiq_op(void *ref, int release)
+{
+	if (!release)
+		set_fiq_c_handler(default_fiq_handler);
+	return 0;
 }
 
 static struct irq_chip cp_intc_irq_chip = {
@@ -116,6 +126,11 @@
 	.set_wake	= cp_intc_set_wake,
 };
 
+static struct fiq_handler cp_intc_fiq = {
+        .name = "cp_intc_fiq",
+        .fiq_op = cp_intc_fiq_op,
+};
+
 void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
 			 u8 *irq_prio)
 {
@@ -125,7 +140,6 @@
 	cp_intc_base = base;
 
 	cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
-	set_fiq_c_handler(default_fiq_handler);
 	/* Disable all host interrupts */
 	cp_intc_write(0, CP_INTC_HOST_ENABLE(0));
 
@@ -141,7 +155,10 @@
 	for (i = 0; i < num_reg; i++)
 		cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i));
 
-	/* Enable nIRQ (what about nFIQ?) */
+	/* Install the default fiq handler */
+	if (claim_fiq(&cp_intc_fiq) == 0)
+		cp_intc_fiq_op(&cp_intc_fiq, 0);
+	/* Enable nIRQ and fiq */
 	cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
 	cp_intc_write(0, CP_INTC_HOST_ENABLE_IDX_SET);
 
@@ -186,30 +203,11 @@
 }
 
 
-void cp_intc_set_channel(unsigned int channel, unsigned int irq)
-{
-  unsigned int index  = (channel >> 2);
-  unsigned int offset = (channel & 0x03) << 3; 
-  unsigned int val;
-
-  val  = cp_intc_read(CP_INTC_CHAN_MAP(index));
-  val &= ~(0xFF << offset);
-  val |= channel << offset;
-
-  cp_intc_write(val, CP_INTC_CHAN_MAP(index));
-}
-
 void cp_intc_fiq_enable(bool enable, unsigned int irq)
 {
   if (enable)
-  {
-    cp_intc_write(0, CP_INTC_HOST_ENABLE_IDX_SET);
     cp_intc_unmask_irq(irq);
-  }
   else
-  {
     cp_intc_mask_irq(irq);
-    cp_intc_write(0, CP_INTC_HOST_ENABLE_IDX_CLR);
-  }
-}
-
+}
+