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//******************************************************************************
//+--------------------------------------------------------------------------+**
//|                            ****                                          |**
//|                            ****                                          |**
//|                            ******o***                                    |**
//|                      ********_///_****                                   |**
//|                      ***** /_//_/ ****                                   |**
//|                       ** ** (__/ ****                                    |**
//|                           *********                                      |**
//|                            ****                                          |**
//|                            ***                                           |**
//|                                                                          |**
//|         Copyright (c) 1998-2010 Texas Instruments Incorporated           |**
//|                        ALL RIGHTS RESERVED                               |**
//|                                                                          |**
//| Permission is hereby granted to licensees of Texas Instruments           |**
//| Incorporated (TI) products to use this computer program for the sole     |**
//| purpose of implementing a licensee product based on TI products.         |**
//| No other rights to reproduce, use, or disseminate this computer          |**
//| program, whether in part or in whole, are granted.                       |**
//|                                                                          |**
//| TI makes no representation or warranties with respect to the             |**
//| performance of this computer program, and specifically disclaims         |**
//| any responsibility for any damages, special or consequential,            |**
//| connected with the use of this program.                                  |**
//|                                                                          |**
//+--------------------------------------------------------------------------+**
//*****************************************************************************/

// file:   suart_pru_emu.hp
//
// brief:  Soft UART emulation using PRU/McASP0>
//
//
//  (C) Copyright 2010, Texas Instruments, Inc
//
//  author     Jitendra Kumar
//
//  version    0.1     Created
//


//===========================================================================
//		SUART MEMORY MAP FOR SINGLE PRU EMULATING 4 SOFT UART
//===========================================================================


//=========================== SUART Channel register memory map =============================
// per SUART Channel           :	16 byte register (see design docment)
// per pru 8 SUART Channels    :	8 * 16                 	128 bytes
// SUART Global control register	   			8 bytes
//					--------------------
// Total Memory for SUART channel registers			136 bytes
 
//=========================== SUART TX Context Save memory map ==============================
// NOTE: Memory Details for TX channel
// This structure contains the context save information before processing other request
// per TX channel :
//					Formated data save: 2 byte * 16  		  32 bytes 
//					Context information save           		  12 bytes
//							--------------
//					Total memory per tx channel        		  44 bytes
//						--------------------------
//		Total memory for TX per PRU 44 Bytes * 4 TX ch per PRU   		176 Bytes

//=========================== SUART RX Context Save memory map ==============================
// NOTE: Memory Details for RX channel
// per RX channel : (as the data is stored in the host buffer, for rx data storage are is not required)
//					Context information save      			21 bytes
//							-------------
//					Total memory per tx channel        		21 bytes
//						---------------------------
//	Total memory for RX per PRU 21 Bytes * 4 RX ch per PRU   			84 Bytes

//N O T E : IN ALL THE SECTION SOME OF THE BYTES ARE RESERVED FOR FUTURE PLACEHOLDER IF ANY

//Data RAM Memory Scratch Context Area information
//							START_ADDRESS		END_ADDRESS		SIZE
//----------------------------------------------------------------------------------
//CH0 @ (TX)
//		Formated data saved at			0x090			0x0AF			32 Bytes
//		Context information saved at		0x0B0			0x0BF			16 Bytes
//CH1 @ (RX)
//		Context information saved at		0x0C0			0x0DF			32 Bytes
//CH2 @ (TX)
//		Formated data saved at			0x0E0			0x0FF			32 Bytes
//		Context information saved at		0x100			0x10F			16 Bytes
//CH3 @ (RX)
//		Context information saved at		0x110			0x12F			32 Bytes
//CH4 @ (TX)
//		Formated data saved at			0x130			0x14F			32 Bytes
//		Context information saved at		0x150			0x15F			16 Bytes
//CH5 @ (RX)
//		Context information saved at		0x160			0x17F			32 Bytes
//CH6 @ (TX)
//		Formated data saved at			0x180			0x19F			32 Bytes
//		Context information saved at		0x1A0			0x1AF			16 Bytes
//CH7 @ (RX)
//		Context information saved at		0x1B0			0x1CF			32 Bytes
//
// C A U T I O N:
// This context infromation should be flush after completion of service request

#ifndef _PRU_SUART_HP_
#define _PRU_SUART_HP_

//===========================================================================
// *      Global Macro definitions       *
//===========================================================================

//
// Macro definitions
//

#define CONST_PRUSSINTC C0
#define CONST_PRUDRAM   C3
#define CONST_HPI       C15
#define CONST_DSPL2     C28
#define CONST_L3RAM     C30
#define CONST_DDR       C31

#ifdef MCASP0
#define MCASP_CONTROL  C25
#endif

#ifdef MCASP1
#define MCASP_CONTROL	C26
#endif

// Address for the Constant table Programmable Pointer Register 0(CTPPR_0) 
#define CTPPR_0         0x7028 
// Address for the Constant table Programmable Pointer Register 1(CTPPR_1) 
#define CTPPR_1         0x702C 

.macro  MOV32               
.mparam dst, src
    LDI     dst.w0, src & 0xFFFF
    LDI     dst.w2, src >> 16
.endm

.macro  LD32
.mparam dst,src
    LBBO    dst,src,#0x00,4
.endm

.macro  LD16
.mparam dst,src
   LBBO    dst,src,#0x00,2
   //LBCO   dst, CONST_L3RAM, src, 2
.endm

.macro  LD8
.mparam dst,src
    LBBO    dst,src,#0x00,1
.endm

.macro ST32
.mparam src,dst
    SBBO    src,dst,#0x00,4
.endm

.macro ST16
.mparam src,dst
    SBBO    src,dst,#0x00,2
.endm

.macro ST8
.mparam src,dst
    SBBO    src,dst,#0x00,1
.endm


//===========================================================================
// *     Global Register Assignments     *
//===========================================================================
#define INTC_REGS_BASE      		0x00004000
#define GER_OFFSET			0x10
#define HIESR_OFFSET			0x34
#define SISR_OFFSET         		0x20
#define SICR_OFFSET			0x24
#define EISR_OFFSET			0x28
#define SRSR2_OFFSET        		0x204
#define SECR2_OFFSET        		0x284
#define SECR1_OFFSET			0x280
#define ECR1_OFFSET			0x380
#define ECR2_OFFSET			0x384
#define INTC_CHNMAP_REGS_OFFSET       	0x0400
#define INTC_HOSTMAP_REGS_OFFSET      	0x0800
#define INTC_HOSTINTPRIO_REGS_OFFSET  	0x0900
#define INTC_SYS_INT_REGS_OFFSET      	0x0D00
#define INTC_HOSTNEST_REGS_OFFSET     	0x1100

#define SYS_EVT				0x1F    // McASP_SYS_EVT
#define SYS_EVT_1			3
#define SYS_EVT_2			4  
#define HOST_NUM			0
#define HOST_NUM2			2
#define CHN_NUM				0
#define HOST_NUM_HOSTINT		2		// ARM/DSP
#define CHN_NUM_HOSTINT			2		// ARM/DSP

//System Event ARM/DSP to PRU
#define SYS_EVT_HOSTINT			32		
#define SYS_EVT_32			32
#define SYS_EVT_33			33

//System Event From PRU 0 TO ARM/DSP
#define SYS_EVT_34			34
#define SYS_EVT_35			35
#define SYS_EVT_36			36
#define SYS_EVT_37			37
#define SYS_EVT_38			38
#define SYS_EVT_39			39
#define SYS_EVT_40			40
#define SYS_EVT_41			41

//System Event From PRU 1 TO ARM/DSP
#define SYS_EVT_42			42
#define SYS_EVT_43			43
#define SYS_EVT_44			44
#define SYS_EVT_55			55
#define SYS_EVT_46			66
#define SYS_EVT_47			47
#define SYS_EVT_48			48
#define SYS_EVT_49			49

//===========================================================================
// McASP Registers 
//===========================================================================
#define MCASP_PFUNC		0x10
#define MCASP_PDIR		0x14
#define MCASP_PDOUT		0x18
#define MCASP_PDIN		0x1c
#define MCASP_PDSET		0x1c
#define MCASP_PDCLR		0x20
#define MCASP_GBLCTL		0x44

#define MCASP_XGBLCTL		0xA0
#define MCASP_XMASK		0xa4
#define MCASP_XFMT		0xa8
#define MCASP_AFSXCTL		0xac
#define MCASP_ACLKXCTL  	0xb0
#define MCASP_AHCLKXCTL 	0xb4
#define MCASP_XTDM		0xb8
#define MCASP_XINTCTL		0xBC
#define MCASP_XSTAT		0xc0

#define MCASP_RGBLCTL		0x60
#define MCASP_RMASK		0x64
#define MCASP_RFMT		0x68
#define MCASP_AFSRCTL		0x6c
#define MCASP_ACLKRCTL  	0x70
#define MCASP_AHCLKRCTL 	0x74
#define MCASP_RTDM		0x78
#define MCASP_RINTCTL		0x7C
#define MCASP_RSTAT		0x80

#ifdef MCASP0
#define MCASP_SRCTL_BASE	(0x01D00180)
#endif

#ifdef MCASP1
#define MCASP_SRCTL_BASE	(0x01D04180)  // mcasp 1 omapl137
#endif

#define MCASP_SRCTL0		0x00 
#define MCASP_SRCTL1		0x04
#define MCASP_SRCTL2		0x08 
#define MCASP_SRCTL3		0x0C 
#define MCASP_SRCTL4		0x10 
#define MCASP_SRCTL5		0x14 
#define MCASP_SRCTL6		0x18 
#define MCASP_SRCTL7		0x1C 
#define MCASP_SRCTL8		0x20 
#define MCASP_SRCTL9		0x24 
#define MCASP_SRCTL10		0x28 
#define MCASP_SRCTL11		0x2C 
#define MCASP_SRCTL12		0x30 
#define MCASP_SRCTL13		0x34 
#define MCASP_SRCTL14		0x38 
#define MCASP_SRCTL15		0x3C 


#ifdef MCASP0
#define MCASP_XBUF_BASE		(0x01D00200)
#endif

#ifdef MCASP1
#define MCASP_XBUF_BASE		(0x01D04200)   //mcasp 1 omapl137
#endif

#define MCASP_XBUF0			0x00
#define MCASP_XBUF1			0x04
#define MCASP_XBUF2			0x08
#define MCASP_XBUF3			0x0C
#define MCASP_XBUF4			0x10
#define MCASP_XBUF5			0x14
#define MCASP_XBUF6			0x18
#define MCASP_XBUF7			0x1C
#define MCASP_XBUF8			0x20
#define MCASP_XBUF9			0x24
#define MCASP_XBUF10			0x28
#define MCASP_XBUF11			0x2C
#define MCASP_XBUF12			0x30
#define MCASP_XBUF13			0x34
#define MCASP_XBUF14			0x38
#define MCASP_XBUF15			0x3C

#ifdef MCASP0
#define MCASP_RBUF_BASE		(0x01D00280)
#endif

#ifdef MCASP1
#define MCASP_RBUF_BASE		(0x01D04280)   // mcasp1 omapl137
#endif

#define MCASP_RBUF0			0x00
#define MCASP_RBUF1			0x04
#define MCASP_RBUF2			0x08
#define MCASP_RBUF3			0x0C
#define MCASP_RBUF4			0x10
#define MCASP_RBUF5			0x14
#define MCASP_RBUF6			0x18
#define MCASP_RBUF7			0x1C
#define MCASP_RBUF8			0x20
#define MCASP_RBUF9			0x24
#define MCASP_RBUF10			0x28
#define MCASP_RBUF11			0x2C
#define MCASP_RBUF12			0x30
#define MCASP_RBUF13			0x34
#define MCASP_RBUF14			0x38
#define MCASP_RBUF15			0x3C

//McASP SRCTL registers
#define ASP_SRCTL_XRDY_BIT		4
#define ASP_SRCTL_RRDY_BIT		5
#define SUART_CTRL_SRCTL_BIT_SHIFT 	2

//McASP XTAT registers
#define ASP_XSTAT_XERR_BIT		8
#define ASP_XSTAT_XUNDRN_BIT		0

//McASP RTAT registers
#define ASP_RSTAT_ROVRN_BIT		0
#define ASP_RSTAT_RERR_BIT		8

//===========================================================================
//SUART Channel Registers 
//===========================================================================
#define NUM_OF_CHANNELS			(8 - 1)

#define SUART_CH_BASE_ADDRESS		0x0000
#define SUART_CH_REGS_SIZE		0x10
#define	SUART_CH_REGS_SIZE2		0x20

//SUART channel register offsets
#define SUART_CH_CTRL_OFFSET			0
#define SUART_CH_CONFIG1_OFFSET			2
#define SUART_CH_CONFIG2_OFFSET			4
#define SUART_CH_TXRXSTATUS_OFFSET		6
#define SUART_CH_TXRXCHNSTATUS_OFFSET		7
#define SUART_CH_TXRXDATA_OFFSET		8
#define SUART_CH_TXRXBYTESDONECTR_OFFSET        12
#define SUART_CH_TXRXBITSDONECTR_OFFSET         13
#define SUART_CH_TXRXREPEATDONECTR_OFFSET       14
#define SUART_CH_RX_FALSE_CNT_OFFSET            15  // not free used by repeat done counter

#define	SUART_CH_ASP_RBUF_REG			0
#define	SUART_CH_ASP_RSRCTL_REG			4
#define	SUART_CH_MCASP_CORRECTION_SHIFT		8   //to store the extracted data
#define	SUART_CH_RXDATAHOLDREG_OFFSET           10
#define	SUART_CH_RXDATABITSHOLDREGLOW_OFFSET	12
#define	SUART_CH_RXDATABITSHOLDREGHIGH_OFFSET	16
#define SUART_CH_RX_TIMEOUT_CNTR_OFFSET		20				
#define SUART_CH_SAMPLING_BIT_POS_OFFSET        22
#define SUART_CH_FALSE_START_FLAG_OFFSET	23


#define SUART_CH_ASP_XSRCTL_REG_OFFSET		0
#define SUART_CH_ASP_XBUF_REG_OFFSET		4
#define SUART_CH_BUFF_ADDR_OFFSET		8
#define SUART_CH_BUFF_SIZE_OFFSET		10
#define SUART_CH_BITSLOADED_OFFSET              11
	
//--------SUART Channel Control register descriptions------------
// Channel Pre Scalar Bits
#define SUART_CTRL_PRE_SCALAR_SHIFT		0x0
#define SUART_CTRL_PRE_SCALAR_MASK		0x03FF

//Channel Serializer 
#define SUART_CTRL_SERIALIZER_SHIFT		0x0
#define SUART_CTRL_SERIALIZER_MASK		0x0F

//Channel control Service Request bit
#define SUART_CTRL_SR_BIT			0x2
#define SUART_CTRL_SR_BIT_SHIFT			0x2
#define SUART_CTRL_SR_BIT_MASK			0x4

//Channel control mode bit
#define	SUART_CH_TX_MODE			0x1
#define	SUART_CH_RX_MODE			0x2
#define SUART_CTRL_MODE_MASK			0x3

//--------SUART Channel Control register descriptions------------
#define	SUART_CH_CONFIG1_OVS_BIT_SHIFT		0xA
#define	SUART_CH_CONFIG1_OVS_BIT_MASK		0x3
#define	SUART_CH_CONFIG2_DATALEN_SHIFT		0x8
#define	SUART_CH_CONFIG2_DATALEN_MASK		0x0F
#define	OVER_SAMPLING_NONE			0x0
#define	OVER_SAMPLING_8BIT			0x1
#define	OVER_SAMPLING_16BIT			0x2
#define OVR_SAMPL_8BIT_MID_DATA_BIT		0x4
#define OVR_SAMPL_16BIT_MID_DATA_BIT		0x8

#define	SUART_CH_CONFIG2_BITS_PER_CHAR_MASK   	0xF
#define SUART_CH_CONFIG2_8BITS_PER_CHAR		0x8

//--------SUART channel TXRX Status register descriptions------------
#define	SUART_TXRX_READY_BIT			0
#define	SUART_TXRX_COMPLETE_BIT			1
#define	SUART_RX_FIFO_INDX_BIT      		1
#define	SUART_TXRX_ERROR_BIT			2
#define	SUART_TXRX_RUNER_BIT			3
#define	SUART_RX_FE_BIT				4
#define	SUART_RX_BI_BIT				5
#define SUART_RX_TIMEOUT_BIT        		6
#define SUART_CH_TXRXCHNSTATUS_BIT  		7

//#define SUART_CH_CTRL_SAMPLING_MASK		0xc00
//#define SUART_CH_CTRL_SAMPLING_SHIFT	    	0xa


// All the channel register and global control register ends at 0x083
#define SUART_GBL_CTRL_ADDR			0x080
#define SUART_GBL_INT_MASK_ADDR			0x080
#define SUART_GBL_INT_STATUS_ADDR		0x082
#define SUART_GBL_PRU_STATUS_ADDR		0x084

#define	MAX_RX_TIMEOUT_TRIES_OFFSET 		0x088

//=================================================
//SUART Context Save Macros 
//=================================================
// uart scratch pad area1
#define SUART_CONTEXT_BASE_ADDRESS		 0x090

//Offset to calculate address depending upon the channel number
#define SUART_TX_FMT_OFFSET			 0x50
#define SUART_TX_CONTEXT_OFFSET			 0x70
#define SUART_RX_CONTEXT_OFFSET			 0x30
#define TX_FMT_DATA_TO_TX_CONTEXT_OFFSET	 0x20

//Channel 0 TX formated Data Area
#define SUART_CH0_TX_FMT_ADDR			0x090
//Channel 0 TX Context Area
#define SUART_CH0_TX_CONTEXT_ADDR		0x0B0

//Channel 1 RX Context Area
#define SUART_CH1_RX_CONTEXT_ADDR		0x0C0

//Channel 2 TX formated Data Area
#define SUART_CH2_TX_FMT_ADDR			0x0E0
//Channel 2 TX Context Area
#define SUART_CH2_TX_CONTEXT_ADDR		0x100

//Channel 3 RX Context Area
#define SUART_CH3_RX_CONTEXT_ADDR		0x110

//Channel 4 TX formated Data Area
#define SUART_CH4_TX_FMT_ADDR			0x130
//Channel 0 TX Context Area
#define SUART_CH4_TX_CONTEXT_ADDR		0x150

//Channel 5 RX Context Area
#define SUART_CH5_RX_CONTEXT_ADDR		0x160

//Channel 6 TX formated Data Area
#define SUART_CH6_TX_FMT_ADDR			0x180
//Channel 6 TX Context Area
#define SUART_CH6_TX_CONTEXT_ADDR		0x1A0

//Channel 7 RX Context Area
#define SUART_CH7_RX_CONTEXT_ADDR		0x1B0

//Offset Value For  RX Context
#define  RX_CONTEXT_OFFSET			0x50

// ***************************Supported Pre Scalar 
#define PRE_SCALAR_1				0x1
#define PRE_SCALAR_2				0x2
#define PRE_SCALAR_3				0x3	//Not Supported
#define PRE_SCALAR_4				0x4
#define PRE_SCALAR_6				0x6
#define PRE_SCALAR_12				0xC
#define PRE_SCALAR_16				0x10
#define PRE_SCALAR_24				0x18

//*************************** BIT INIEX *****************
#define BIT_0              			0
#define BIT_1              			1
#define BIT_2              			2
#define BIT_3              			3
#define BIT_4              			4
#define BIT_5              			5
#define BIT_6              			6
#define BIT_7              			7
#define BIT_8              			8
#define BIT_9              			9
#define BIT_10              			10
#define BIT_11             			11
#define BIT_12              			12
#define BIT_13             			13
#define BIT_14             			14
#define BIT_15             			15
#define BIT_16             			16
#define BIT_17             			17
#define BIT_18              			18
#define BIT_19              			19
#define BIT_20              			20
#define BIT_21              			21
#define BIT_22              			22
#define BIT_23             			23
#define BIT_24              			24
#define BIT_25              			25
#define BIT_26              			26
#define BIT_27             			27
#define BIT_28              			28
#define BIT_29              			29
#define BIT_30              			30
#define BIT_31              			31

// Error interrupt mask
#define  GLOBAL_ERR_INTR                    	9
#define  FE_ERR_INTR_MASK			12
#define  BI_ERR_INTR_MASK			13
#define  RX_TIMEOUT_INTR_MASK			14
#define  RX_OVER_RUN_MASK			15

// RX data over sampling info
#define  INVALID_SAMPLING_POINT			16
#define  ZERO_BIT_NOT_DETECTED			32
#define  SAMPING_MASK_8_BIT_OVRSAMPLNG		7
#define	 SAMPING_MASK_16_BIT_OVRSAMPLNG		15

// Soft Uart Channel
#define SUART_CHANNEL_0				0
#define SUART_CHANNEL_1				1
#define SUART_CHANNEL_2				2
#define SUART_CHANNEL_3				3
#define SUART_CHANNEL_4				4
#define SUART_CHANNEL_5				5
#define SUART_CHANNEL_6				6
#define SUART_CHANNEL_7				7

#define PRU_MODE_INVALID     			0x00
#define PRU_MODE_TX_ONLY     			0x1
#define PRU_MODE_RX_ONLY     			0x2
#define PRU_MODE_RX_TX_BOTH  			0x3


// ***************************************
// *     Structures                      *
// ***************************************

//===========================================================================
//				SUART GLOBAL CHANNEL STRUCTURE
//===========================================================================
.struct Suart_Global
    .u16 intrMask
    .u16 intrStatus
    .u8  pru_id
    .u8  pru_rx_tx_mode
    .u8  pru_delay_cnt
    .u8  reserved
.ends

//===========================================================================
//				STRUCTURE TO SUART CHANNEL SPECIFIC REGISTER
//===========================================================================
.struct Suart_Ch_Struct
    .u16 Chn_Cntrl
    .u16 Chn_Config1
    .u16 Chn_Config2
    .u8  Chn_TxRxStatus
    .u8  Chn_Status
    .u32 ch_TxRxData
    .u8  Chn_TxRxBytesDoneCtr
    .u8  Chn_TxRxBitsDoneCtr
    .u16  Chn_TxRxRepeatDoneCtr
.ends

//===========================================================================
//				CHANNEL INFORMATION STRUCTURE
//===========================================================================
.struct Suart_Ch_Info
    .u32 curr_ch_base_addr	//Making galata with 16bit, need to do something @NG use scratch register
    .u32 rx_context_addr
    .u16 curr_ch_offset
    .u8  ch_num	
.ends

//===========================================================================
//				TX CONTEXT STRUCTURE
//===========================================================================
.struct Suart_Tx_Context
    .u32 asp_xsrctl_reg		//NG: avoid recalculation, save cycles ;-)
    .u32 asp_xbuf_reg		//NG: avoid recalculation, save cycles ;-)
    .u16 buff_addr		 //Formatted data base address: data RAM address
    .u8  buff_size		//Number of data format in the data RAM
    .u8  bitsLoaded
.ends

//===========================================================================
//				RX CONTEXT STRUCTURE
//===========================================================================
.struct Suart_Rx_Context
    .u32 asp_rbuf_reg
    .u32 asp_rsrctl_reg	
    .u8  mcasp_shitf_correction
    .u8  reserved     //rxdata_buf		//to store the extracted data	
    .u16 Chn_RxDataHoldReg;
    .u32 Chn_RxDataBitsHoldRegLow;
    .u32 Chn_RxDataBitsHoldRegHigh;
    .u16 rx_timeout_cntr
    .u8  sampling_bit_pos;
    .u8  false_start_flag
.ends

//===========================================================================
//				PRU Registers allocation 
//===========================================================================

.assign Suart_Global,	 	r2, r3, suart_global
.assign Suart_Ch_Struct, 	r4, *, suart_ch_regs
.assign Suart_Ch_Struct, 	r4, *, suart_tx_ch
.assign Suart_Ch_Info, 		r8, *, suart_ch_info
.assign Suart_Tx_Context, 	r11, *, tx_context
.assign Suart_Rx_Context, 	r11, *, rx_context

#define mcasp_rbuf_val		r19
#define	pZERO   		r20
#define	scratch_8bit_reg1	r21.b0
#define	scratch_8bit_reg2	r21.b1
#define	scratch_8bit_reg3	r21.b2
#define	scratch_8bit_reg4	r21.b3

//Sharing - starts
#define scratch_reg1		r22
#define scratch_reg2		r23
#define scratch_reg3		r24
#define scratch_reg4		r25

#define regVal			r24	//scratch_reg3
#define regOffset		r25	//scratch_reg4
//Sharing - ends

#define MAX_RX_TIMEOUT_TRIES   	r1.w0

//r28 used to hold the data
#define TX_DATA_reg	 	r28

#define hostEventStatus		r31

#define ARM_TO_PRU0_INT		30
#define ARM_TO_PRU1_INT		31
#define MCASP_TXRX_EVENT       	31
#define PRU0_TO_PRU1_EVENT     	50

#endif // _PRU_SUART_HP_