--- a
+++ b/modules/lms2012/d_uart/Linuxmod_AM1808/pru-firmware-05-31-2011-1423-v3.0/pru/firmware/can/PRU_CAN_Emulation_Tx.hp
@@ -0,0 +1,211 @@
+// Source: PRU_CAN_Emulation_Tx.hp
+// Revision: 1.0
+//
+
+#ifndef _PRU_CAN_EMULATION_TX_HP_
+#define _PRU_CAN_EMULATION_TX_HP_
+
+
+// ***************************************
+// *      Global Macro definitions       *
+// ***************************************
+
+#define HOST_NUM	2
+#define CHN_NUM		2
+
+#define CONST_PRUSSINTC C0
+#define CONST_PRUDRAM   C3
+#define CONST_HPI       C15
+#define CONST_DSPL2     C28
+#define CONST_L3RAM     C30
+#define CONST_DDR       C31
+
+#define SYS_EVT_DSPARM_PRU_TX  					32
+#define SYS_EVT_PRU_DSPARM_TX					33
+#define TRANSMIT_DSPARM_TO_PRU_HOST_NUM       	0
+#define TRANSMIT_DSPARM_TO_PRU_CHN_NUM        	0
+#define TRANSMIT_PRU_TO_DSPARM_HOST_NUM       	3
+#define TRANSMIT_PRU_TO_DSPARM_CHN_NUM        	3
+
+#define GER_OFFSET        			0x10
+#define HIESR_OFFSET      			0x34
+#define SICR_OFFSET       			0x24
+#define EISR_OFFSET       			0x28
+#define SRSR2_OFFSET    			0x204
+#define SECR1_OFFSET				0x4280
+#define SECR2_OFFSET    			0x4284
+#define ECR1_OFFSET      			0x4380
+#define ECR2_OFFSET      			0x4384
+#define	INTCTL_BASE 				0x01c3
+
+#define ELEVEN_CONSECUTIVE_HIGH_BIT		11
+#define BUS_OFF_RESET_CNT_128			128
+#define CAN_PASSIVE_ERR_BIT				3
+#define CAN_BUS_OFF_ERR_BIT				4
+#define CAN_INTR_ERR_BIT				14
+#define CAN_ARBTR_ERR_BIT				4
+#define PRU_CAN_ERROR_ACTIVE			128
+#define PRU_CAN_BUS_OFF_ERR_CNT			255
+#define END_OF_FRAME_CNT				7
+#define CAN_STD_FRAME_ID				11
+#define CAN_EXTD_FRAME_ID				29
+#define ARBTR_RETRY_CNT					3
+
+#define ERR_FRAME_LENGTH				6
+#define	ERR_DELMTR_LEN					8
+
+#define EventStatus     				r31
+#define SystemEventRegister				r31
+#define TempRegister					r8
+#define ShiftRegister					r9
+#define MailboxShiftRegister			r10
+#define RegisterOffset       			r15
+#define RegisterValue        			r16
+#define BitCounter        				r17
+#define CurrentMailbox					r18
+#define BitStuffCounter					r19
+#define CanFrame						r20
+#define CanCurrentState					r21
+#define DataCounter						r22
+#define BitsToSendCntr					r23
+#define DelayCntr						r24
+#define Identifier						r25
+#define CRCFrame						r26
+#define CRC_TempVar						r27
+#define CRC_Input						r28
+
+.macro  MOV32               
+.mparam dst, src
+    MOV     dst.w0, src & 0xFFFF
+    MOV     dst.w2, src >> 16
+.endm
+
+.macro  LD32
+.mparam dst,src
+    LBBO    dst,src,#0x00,4
+.endm
+
+.macro  LD16
+.mparam dst,src
+    LBBO    dst,src,#0x00,2
+.endm
+
+.macro  LD8
+.mparam dst,src
+    LBBO    dst,src,#0x00,1
+.endm
+
+.macro ST32
+.mparam src,dst
+    SBBO    src,dst,#0x00,4
+.endm
+
+.macro ST16
+.mparam src,dst
+    SBBO    src,dst,#0x00,2
+.endm
+
+.macro ST8
+.mparam src,dst
+    SBBO    src,dst,#0x00,1
+.endm
+
+.macro	GPIO_SET
+.mparam bitNum
+   SET	r30, r30, bitNum
+.endm
+
+.macro	GPIO_CLEAR
+.mparam bitNum
+   CLR	r30, r30, bitNum
+.endm
+
+.macro	DELAY_LOOP
+.mparam Delay
+mov 	DelayMacCntr,Delay
+QBEQ  EXIT,DelayMacCntr,0
+LOOP:
+  SUB	DelayMacCntr, DelayMacCntr, 1
+  QBEQ  EXIT,DelayMacCntr,0
+  JMP	LOOP
+EXIT:
+.endm
+
+#define GPIO_TX_BIT								15
+#define GPIO_RX_BIT								0
+#define GPIO_TX_MIRROR_BIT						18
+
+#define PRU_CAN_TX_GLOBAL_CONTROL_REGISTER  	0x0
+#define PRU_CAN_TX_GLOBAL_STATUS_REGISTER  		0x4
+#define PRU_CAN_TX_INTERRUPT_MASK_REGISTER  	0x8
+#define PRU_CAN_TX_INTERRUPT_STATUS_REGISTER  	0xC
+#define PRU_CAN_TX_MAILBOX0_STATUS_REGISTER  	0x10
+#define PRU_CAN_TX_MAILBOX1_STATUS_REGISTER  	0x14
+#define PRU_CAN_TX_MAILBOX2_STATUS_REGISTER  	0x18
+#define PRU_CAN_TX_MAILBOX3_STATUS_REGISTER  	0x1C
+#define PRU_CAN_TX_MAILBOX4_STATUS_REGISTER  	0x20
+#define PRU_CAN_TX_MAILBOX5_STATUS_REGISTER  	0x24
+#define PRU_CAN_TX_MAILBOX6_STATUS_REGISTER  	0x28
+#define PRU_CAN_TX_MAILBOX7_STATUS_REGISTER  	0x2C
+#define PRU_CAN_TX_ERROR_COUNTER_REGISTER  		0x30
+#define PRU_CAN_TX_TIMING_REGISTER  			0x34
+#define PRU_CAN_TX_CLOCK_BRP_REGISTER  			0x38
+
+#define PRU_CAN_RX_GLOBAL_STATUS_REGISTER  		(0x2004)
+
+#define TMR_REGS        			0x01F0C000
+#define TMR_TIM12_OFFSET  			0x10
+#define TMR_PRD12_OFFSET  			0x18
+#define TMR_TCR_OFFSET    			0x20
+#define TMR_TGCR_OFFSET   			0x24
+#define TMR_REL12_OFFSET  			0x34
+#define TMR_INTCTL_OFFSET 			0x44
+#define TIMER12_MODE      			0x0080
+#define TIME_CONST        			1248
+#define TIMER_SYS_EVT         		18    // T64P0_TINT12_SYS_EVT
+
+#define PRU_CAN_TX_MAILBOX0	 		0x40
+#define PRU_CAN_TX_MAILBOX1	 		PRU_CAN_TX_MAILBOX0 + 0x10
+#define PRU_CAN_TX_MAILBOX2	 		PRU_CAN_TX_MAILBOX1 + 0x10
+#define PRU_CAN_TX_MAILBOX3	 		PRU_CAN_TX_MAILBOX2 + 0x10
+#define PRU_CAN_TX_MAILBOX4	 		PRU_CAN_TX_MAILBOX3 + 0x10
+#define PRU_CAN_TX_MAILBOX5	 		PRU_CAN_TX_MAILBOX4 + 0x10
+#define PRU_CAN_TX_MAILBOX6	 		PRU_CAN_TX_MAILBOX5 + 0x10
+#define PRU_CAN_TX_MAILBOX7	 		PRU_CAN_TX_MAILBOX6 + 0x10
+
+#define PRU_CAN_TIMING_VAL_TX			0xC0
+#define PRU_CAN_TIMING_VAL_TX_SJW		0xC4
+#define PRU_CAN_TRANSMIT_FRAME			0xC8
+#define PRU_CAN_CRC_FRAME				0x10A
+#define PRU_CAN_RX_INITIATION			0x110
+
+#define PRU_CAN_TX_BUS_AQUIRED			0x114
+
+#define CAN_ACK_FAILED					0xE
+#define CAN_ARBTR_FAIL					0xD
+#define CAN_BIT_ERROR					0xC
+#define	CAN_TRANSMISSION_SUCCESS		0xA
+
+#define CAN_STD_ID				1
+#define CAN_EXTD_ID				2
+
+#define PRU_CAN_RX_ERROR_COUNTER_REGISTER	0x2034
+
+.struct CAN_MAIL_BOX_STRUCTURE
+
+	.u16 u16CANExtendedIdentifier
+	.u16 u16CANBaseIdentifier
+	.u8  u8CANdata0
+	.u8  u8CANdata1
+	.u8  u8CANdata2
+	.u8  u8CANdata3
+	.u8  u8CANdata4
+	.u8  u8CANdata5
+	.u8  u8CANdata6
+	.u8  u8CANdata7
+	.u16 u16CANdataLength
+	.u16 u16CANCRC
+.ends
+
+#endif
+