Just a few days ago I fiddled with the thought to create a CPU within ktechlab. But after a few minutes of fiddling I noticed an AND-port that had 2 high-imputs but still had a low-output :(.

On Tue, May 26, 2009 at 11:42 PM, Alan Grimes <agrimes@speakeasy.net> wrote:
One key benchmark for the maturity of this project would be the ability
to simulate an entire CPU.

I fiddled around with that today and came to the following wishlist:

1. We need "tri-state" logic,  (High, Low, and Z where Z is "High

2. We need the option to be able to configure any component so that it
can use buses instead of discreet pins. This is indispensable when
talking about any device with more

3. We need to move the logic config out of the global configuration and
make it a per-part setting, possibly even per-pin deal, We should then
implement a logic config database with the correct parameters for all of
the common logic families.

Unfortunately, the concept of an ALU is somewhat fuzzy, though it should
be possible to implement a fairly general model that will work for most

An excellent CPU to try to implement is the core of the F21 from
www.ultratechnology.com =)

New president: Here we go again...
Chemistry.com: A total rip-off.
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