[Iverilog-devel] Compiling nested scopes

[Stephen W. <st...@ic...>]

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It looks like pr1887299 has pointed out a design flaw in how
scope hierarchy is managed at parse time. The problem there is
caused by a nested scope (a user defined function in this case)
being defined within a generate case. The Xilinx supplied code
defines a function within a generated case. Yuck!

So my next big task is going to be to rework how nested scopes
are handled at the pform level. This'll be a fairly big task
what will tough pform.cc and parse.y where nested scopes are
handled, as well as where the items put in those scopes (wires
et al) are handled.

So beware if you are working in any of those areas!
- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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