From: Cary R. <cygcary@ya...> - 2011-03-15 22:25:43
It's been a while since I sent an update on the vlog95 converter so here is the
Module ports are mostly working.
Selects in a CA are partially done.
Variable bit selects of a parameter in a CA are missing.
Generate constructs are missing.
Specify blocks are missing.
Various other bugs.
At this time most of the test suite can be converted correctly. It even converts
most of the unsigned VHDL examples Steve just submitted. Since module ports are
mostly working I'd consider this late alpha code. I'm still not looking for bug
reports since there are a large number of known bugs/missing functionality, but
if you are interested, now would be a good time to grab the latest development
code from git to see if your code can be converted or not. I'd be interested in
I'm also planning to add a flag that will allow the converter to emit code that
supports signed. Basically it will just emit the signed keyword and the
$signed()/$unsigned() system functions. The signed keyword is easy. The system
functions are a bit more complicated since they must be divined from the
expressions. I'm not sure if the >>> operator will be included in this. I need
to investigate if it is normally allowed if signed is allowed.
Given the recent VHDL work it may make sense to modify this converter to be a
more general Verilog converter that outputs 1995, 1995+signed and 2005
compatible code. Thoughts on this would be appreciated
I'm expecting my focus to be fixing bugs, adding the signed flag and looking at
what's needed to add support for the generate constructs.
Here is a brief update on the vlog95 converter that I am working on.
I have recently fixed a few bugs in both the converter and the compiler and added code to handle all the SystemVerilog constructs Steve added since the last time I worked on the converter.
I have audited the tests and verified that most of the tests are working or are only generating an appropriate not supported message. The major places where incorrect results are given without a warning are the following:
- Code to figure out where $signed() or $unsigned() are needed has not been implemented.
- Specify blocks are silently ignored.
- SystemVerilog two state variables obviously have the wrong initial value when converted to four state variables.
I am working on a short list of unclassified failures, translation errors and asserts. My short term goal is to fix these problem or at least classify them and then work on adding $signed() and $unsigned() support. After that I plan to look at detecting a specify block was ignored and then figure out how to translate the generate tests. Longer term inout ports need to be translated and there are some limitations in converting selects in a continuous assignment that need to be removed.